公开(公告)号：US20160372606A1

公开(公告)日：2016-12-22

申请号：US15182812

申请日：2016-06-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Daigo ITO ,  Daisuke MATSUBAYASHI ,  Masaharu NAGAI ,  Yoshiaki YAMAMOTO ,  Takashi HAMADA ,  Yutaka OKAZAKI ,  Shinya SASAGAWA ,  Motomu KURATA ,  Naoto YAMADE

IPC: H01L29/786 ,  H01L27/12 ,  H01L21/425 ,  H01L21/46 ,  H01L29/04 ,  H01L29/66

CPC classification number: H01L29/78693 ,  H01L21/425 ,  H01L21/46 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1262 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7782 ,  H01L29/7854 ,  H01L29/7855 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor layer over the first metal oxide layer, a second metal oxide layer over the oxide semiconductor layer, a gate insulating layer over the second metal oxide layer, a second insulating layer over the second metal oxide layer, and a gate electrode layer over the gate insulating layer. The gate insulating layer includes a region in contact with a side surface of the gate electrode layer. The second insulating layer includes a region in contact with the gate insulating layer. The oxide semiconductor layer includes first to third regions. The first region includes a region overlapping with the gate electrode layer. The second region, which is between the first and third regions, includes a region overlapping with the gate insulating layer or the second insulating layer. The second and third regions each include a region containing an element N (N is phosphorus, argon, or xenon).

Abstract translation: 一种半导体器件包括：衬底上的第一绝缘层，第一绝缘层上的第一金属氧化物层，第一金属氧化物层上的氧化物半导体层，氧化物半导体层上的第二金属氧化物层， 第二金属氧化物层，第二金属氧化物层上的第二绝缘层，以及栅极绝缘层上的栅电极层。 栅极绝缘层包括与栅电极层的侧表面接触的区域。 第二绝缘层包括与栅极绝缘层接触的区域。 氧化物半导体层包括第一至第三区域。 第一区域包括与栅电极层重叠的区域。 位于第一和第三区域之间的第二区域包括与栅极绝缘层或第二绝缘层重叠的区域。 第二和第三区域各自包括含有元素N（N是磷，氩或氙）的区域。

公开(公告)号：US20140103409A1

公开(公告)日：2014-04-17

申请号：US14134047

申请日：2013-12-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tetsuya KAKEHATA ,  Hideto OHNUMA ,  Yoshiaki YAMAMOTO ,  Kenichiro MAKINO

IPC: H01L29/06 ,  H01L29/78 ,  H01L31/0352

CPC classification number: H01L27/1218 ,  H01L21/76254 ,  H01L27/1214 ,  H01L27/1266 ,  H01L29/0649 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/78603 ,  H01L31/0352

Abstract: An object is to provide an SOI substrate provided with a semiconductor layer which can be used practically even when a glass substrate is used as a base substrate. Another object is to provide a semiconductor device having high reliability using such an SOI substrate. An altered layer is formed on at least one surface of a glass substrate used as a base substrate of an SOI substrate to form the SOI substrate. The altered layer is formed on at least the one surface of the glass substrate by cleaning the glass substrate with solution including hydrochloric acid, sulfuric acid or nitric acid. The altered layer has a higher proportion of silicon oxide in its composition and a lower density than the glass substrate.

Abstract translation: 本发明的目的是提供一种具有半导体层的SOI衬底，即使在使用玻璃衬底作为基底衬底时也可以实际使用。 另一个目的是提供一种使用这种SOI衬底具有高可靠性的半导体器件。 在用作SOI衬底的基底衬底的玻璃衬底的至少一个表面上形成改变的层，以形成SOI衬底。 通过用包括盐酸，硫酸或硝酸的溶液清洗玻璃基板，在玻璃基板的至少一个表面上形成改变的层。 改变的层在其组成中具有较高比例的氧化硅，并且具有比玻璃基底更低的密度。

公开(公告)号：US20170288064A1

公开(公告)日：2017-10-05

申请号：US15628699

申请日：2017-06-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Daigo ITO ,  Daisuke MATSUBAYASHI ,  Masaharu NAGAI ,  Yoshiaki YAMAMOTO ,  Takashi HAMADA ,  Yutaka OKAZAKI ,  Shinya SASAGAWA ,  Motomu KURATA ,  Naoto YAMADE

IPC: H01L29/786 ,  H01L27/12 ,  H01L21/46 ,  H01L29/66 ,  H01L21/425

CPC classification number: H01L29/78693 ,  H01L21/425 ,  H01L21/46 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1262 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7782 ,  H01L29/7854 ,  H01L29/7855 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor layer over the first metal oxide layer, a second metal oxide layer over the oxide semiconductor layer, a gate insulating layer over the second metal oxide layer, a second insulating layer over the second metal oxide layer, and a gate electrode layer over the gate insulating layer. The gate insulating layer includes a region in contact with a side surface of the gate electrode layer. The second insulating layer includes a region in contact with the gate insulating layer. The oxide semiconductor layer includes first to third regions. The first region includes a region overlapping with the gate electrode layer. The second region, which is between the first and third regions, includes a region overlapping with the gate insulating layer or the second insulating layer. The second and third regions each include a region containing an element N (N is phosphorus, argon, or xenon).