公开(公告)号：US5812521A

公开(公告)日：1998-09-22

申请号：US674098

申请日：1996-07-01

申请人： Sheldon Bernard Levenstein ,  Nghia Van Phan

发明人： Sheldon Bernard Levenstein ,  Nghia Van Phan

IPC分类号： G06F7/50 ,  G06F7/508

CPC分类号： G06F7/508

摘要： A parallel static adder for adding two n-bit operands, the adder including half-sum circuitry, summing circuitry, and carry look-ahead circuitry. The half-sum circuitry receives a pair of same-order bits from the two n-bit operands, and generates a plurality of half-sum signals for each of the pairs of same-order bits. The summing circuit adds a corresponding half-sum signal to a carry signal from a preceding lower order summing circuit. The carry look-ahead circuit generates a carry signal for higher order summing circuits. Each of the carry look-ahead circuits includes a plurality of logic arrays, each comprising one or more field effect devices coupled in parallel between a first node and a second node, where each of the field effect devices has a gate input to receive lower order addend and augend bits in accordance with a predetermined carry look-ahead equation. The carry look-ahead logic further includes a plurality of bipolar devices, coupled in parallel between a supply voltage and an output node, where each has a base terminal coupled to one of the first nodes of the plurality of field effect devices to provide a sum term of the predetermined sum-of-products at the output node.

摘要翻译： 一个用于加上两个n位操作数的并行静态加法器，加法器包括半和电路，求和电路和进位查找电路。 半和电路从两个n位操作数接收一对相同次序的位，并且为每一对相同位数生成多个半和信号。 加法电路将相应的半和信号加到来自前一个低阶求和电路的进位信号。 进位预先电路为较高阶求和电路产生进位信号。 每个进位先行电路包括多个逻辑阵列，每个逻辑阵列包括在第一节点和第二节点之间并联耦合的一个或多个场效应装置，其中每个场效应装置具有用于接收较低阶的门输入 根据预定的携带查找方程来加数和加数位。 携带预读逻辑还包括多个双极器件，并联耦合在电源电压和输出节点之间，其中每个都具有耦合到多个场效应器件中的第一个节点之一的基极以提供总和 在输出节点处的预定总和乘积的项。

公开(公告)号：US06205063B1

公开(公告)日：2001-03-20

申请号：US09140031

申请日：1998-08-26

申请人： Anthony Gus Aipperspach ,  Sheldon Bernard Levenstein

发明人： Anthony Gus Aipperspach ,  Sheldon Bernard Levenstein

IPC分类号： G11C700

CPC分类号： G11C29/787 ,  G11C29/802 ,  G11C29/812

摘要： Defects in memory circuit (100) are efficiently corrected by selectively blowing fuses in a first plurality of fuses to describe a cell location of a defective cell within any of several memory array portions (110). Fuses in a second plurality of fuses are blown to describe indicate the particular memory array portion (112) containing the defective memory cell. During operation of the memory circuit (100), the cell location is forwarded to the memory array portion (112) containing the defective memory cell and a redundant memory cell (206) is used for data storage at the memory array portion (112) having a defective memory cell.

摘要翻译： 存储器电路（100）中的缺陷通过有选择地在第一多个保险丝中熔断以描述几个存储器阵列部分（110）中的任一个内的有缺陷的单元的单元位置而被有效地校正。 熔断第二多个保险丝中的保险丝被熔断以描述指示包含有缺陷存储器单元的特定存储器阵列部分（112）。 在存储器电路（100）的操作期间，单元位置被转发到包含有缺陷存储单元的存储器阵列部分（112），并且冗余存储单元（206）被用于在存储器阵列部分（112）处的数据存储， 有缺陷的存储单元。

公开(公告)号：US5790838A

公开(公告)日：1998-08-04

申请号：US700263

申请日：1996-08-20

申请人： John David Irish ,  Charles Luther Johnson ,  David John Krolak ,  Sheldon Bernard Levenstein

发明人： John David Irish ,  Charles Luther Johnson ,  David John Krolak ,  Sheldon Bernard Levenstein

IPC分类号： G11C7/10 ,  G06F1/04

CPC分类号： G11C7/1039 ,  G11C7/1072

摘要： According to the present invention, a pipelined SRAM structure and clocking method is disclosed. The SRAM interface and clocking method are specifically intended for use with Level 2 and Level 3 cache SRAM memory devices. In the present invention, the oscillator that generates the clock signal for the CPU is also used to generate the clock signals for all of the other components that interface with the SRAM. Each of the generated clock signals are dependant on the same clock event, allowing the clock speed to be decreased for testing or debugging while maintaining higher speed clock edge relationships. The various clock signals that are generated from the oscillator are used to cycle-steal time from multiple cycles. This technique allows sub-5 nanosecond (nS) access to Level 2 and Level 3 cache memory devices that have access times greater than 5 nS.

摘要翻译： 根据本发明，公开了流水线SRAM结构和计时方法。 SRAM接口和时钟方法专门用于2级和3级缓存SRAM存储器件。 在本发明中，生成用于CPU的时钟信号的振荡器也用于生成与SRAM接口的所有其它组件的时钟信号。 每个生成的时钟信号都取决于相同的时钟事件，允许降低时钟速度以进行测试或调试，同时保持更高速度的时钟边缘关系。 从振荡器产生的各种时钟信号用于从多个周期循环窃取时间。 这种技术允许5纳秒（nS）访问访问次数大于5 nS的2级和3级高速缓存存储器设备。

公开(公告)号：US6105051A

公开(公告)日：2000-08-15

申请号：US956875

申请日：1997-10-23

申请人： John Michael Borkenhagen ,  Richard James Eickemeyer ,  William Thomas Flynn ,  Steven R. Kunkel ,  Sheldon Bernard Levenstein ,  Andrew Henry Wottreng

发明人： John Michael Borkenhagen ,  Richard James Eickemeyer ,  William Thomas Flynn ,  Steven R. Kunkel ,  Sheldon Bernard Levenstein ,  Andrew Henry Wottreng

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F9/00

CPC分类号： G06F9/4843 ,  G06F9/3009 ,  G06F9/3851

摘要： A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread will occur. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register to prevent repetitive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a software manager capable of changing the priority of the different threads and thus superseding thread switch events.

摘要翻译： 用于在数据处理系统中执行计算机处理操作的系统和方法包括多线程处理器和线程切换逻辑。 多线程处理器能够在可独立执行的两条或更多条指令线之间进行切换。 每个线程根据执行状态在线程状态寄存器中具有相应的状态。 线程开关逻辑包含一个线程开关控制寄存器，用于存储发生线程的条件。 线程开关逻辑具有超时寄存器，当多线程处理器中的活动线程的执行超过可编程时间段时，强制执行线程切换。 线程开关逻辑还具有前进进程计数寄存器，以防止多线程处理器中的线程之间的重复线程切换。 线程切换逻辑还响应于能够改变不同线程的优先级并从而取代线程切换事件的软件管理器。

公开(公告)号：US06567839B1

公开(公告)日：2003-05-20

申请号：US08957002

申请日：1997-10-23

申请人： John Michael Borkenhagen ,  Richard James Eickemeyer ,  William Thomas Flynn ,  Sheldon Bernard Levenstein ,  Andrew Henry Wottreng

发明人： John Michael Borkenhagen ,  Richard James Eickemeyer ,  William Thomas Flynn ,  Sheldon Bernard Levenstein ,  Andrew Henry Wottreng

IPC分类号： G06F900

CPC分类号： G06F9/4843 ,  G06F9/3009 ,  G06F9/3851

摘要： A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread switch can occur. Upon the occurrence of a thread switch event, the state and priority of all threads are dynamically interrogated to determine which thread should be the active thread executing the processor. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register to prevent repetitive unproductive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a thread switch manager capable of changing the priority of the different threads and thus superseding thread switch events.

摘要翻译： 用于在数据处理系统中执行计算机处理操作的系统和方法包括多线程处理器和线程切换逻辑。 多线程处理器能够在可独立执行的两条或更多条指令线之间进行切换。 每个线程根据执行状态在线程状态寄存器中具有相应的状态。 线程开关逻辑包含一个线程开关控制寄存器，用于存储可以发生线程切换的条件。 在发生线程切换事件时，动态询问所有线程的状态和优先级，以确定哪个线程应该是执行处理器的主动线程。 线程开关逻辑具有超时寄存器，当多线程处理器中的活动线程的执行超过可编程时间段时，强制执行线程切换。 线程切换逻辑还具有前向进度计数寄存器，以防止多线程处理器中的线程之间的重复无效线程切换。 线程开关逻辑还响应于能够改变不同线程的优先级并因此取代线程切换事件的线程切换管理器。

公开(公告)号：US06557084B2

公开(公告)日：2003-04-29

申请号：US09351654

申请日：1999-07-13

申请人： Donald Lee Freerksen ,  Sheldon Bernard Levenstein ,  Gary Michael Lippert

发明人： Donald Lee Freerksen ,  Sheldon Bernard Levenstein ,  Gary Michael Lippert

IPC分类号： G06F1200

CPC分类号： G06F12/0831

摘要： According to the present invention, an apparatus and method for improving reads from and writes to shared memory locations is disclosed. By giving writes priority over reads, the current invention can decrease the time associated with certain sequences of reads from and writes to shared memory locations. In particular, load-invalidate-load sequences are changed to load—load sequences with the current invention. Furthermore, contention for a shared memory location will be reduced in particular situations when using the current invention.

摘要翻译： 根据本发明，公开了一种用于改善对共享存储器位置的读取和写入的装置和方法。 通过给予对读取优先的写入，本发明可以减少与从共享存储器位置读取和写入的某些顺序相关联的时间。 特别地，利用本发明，将负载无效负载序列改变为负载负载序列。 此外，在使用本发明的特定情况下，共享存储器位置的争用将会减少。

公开(公告)号：US6138209A

公开(公告)日：2000-10-24

申请号：US924272

申请日：1997-09-05

申请人： David John Krolak ,  Sheldon Bernard Levenstein

发明人： David John Krolak ,  Sheldon Bernard Levenstein

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F12/00

CPC分类号： G06F12/0864 ,  G06F12/1054 ,  G06F12/0897 ,  G06F2212/601 ,  G06F2212/6082

摘要： A data processing system and method thereof utilize a unique cache architecture that performs class prediction in a multi-way set associative cache during either or both of handling a memory access request by an anterior cache and translating a memory access request to an addressing format compatible with the multi-way set associative cache. Class prediction may be performed using a class predict data structure with a plurality of predict array elements partitioned into sub-arrays that is accessed using a hashing algorithm to retrieve selected sub-arrays. In addition, a master/slave class predict architecture may be utilized to permit concurrent access to class predict information by multiple memory access request sources. Moreover, a cache may be configured to operate in multiple associativity modes by selectively utilizing either class predict information or address information related to a memory access request in the generation of an index into the cache data array.

摘要翻译： 数据处理系统及其方法利用独特的高速缓存架构，其在由前缓存处理存储器访问请求的任一者或两者中的一个或两者中在多路组关联高速缓存中执行类预测，并将存储器访问请求转换为与 多路组合关联缓存。 可以使用具有被划分为子阵列的多个预测阵列元素的类预测数据结构来执行类预测，所述子阵列使用散列算法来访问以检索所选择的子阵列。 此外，可以利用主/从类预测架构来允许通过多个存储器访问请求源同时访问类预测信息。 此外，高速缓存可以被配置为在多个关联模式中操作，通过在向高速缓存数据阵列生成索引时选择性地利用与存储器访问请求相关的类预测信息或地址信息。

公开(公告)号：US5897662A

公开(公告)日：1999-04-27

申请号：US517759

申请日：1995-08-18

申请人： Michael Joseph Corrigan ,  Sheldon Bernard Levenstein ,  Terrence James Stewart

发明人： Michael Joseph Corrigan ,  Sheldon Bernard Levenstein ,  Terrence James Stewart

IPC分类号： G06F12/10 ,  G06F12/02

CPC分类号： G06F12/1009

摘要： It is known that virtual memory segments that are allocated together tend to be used together. With existing sequential address allocation mechanisms, this in turn means that programs tend to end up using the same set or sets of virtual segment addresses (i.e., in the same minitable or minitables), which, as mentioned, leads to increased address translation time because of clumping. The address allocation mechanism of the present invention reduces clumping by allocating virtual segment addresses in a pseudo-random order. This decreases the likelihood that virtual segment addresses that are allocated together end up in the same set or sets of virtual segment addresses within the address translation table.

摘要翻译： 已知分配在一起的虚拟存储器段一起被一起使用。 使用现有的顺序地址分配机制，这又意味着程序倾向于最终使用相同的虚拟段地址集合（即，在相同的最小或最小值）中，如上所述，这些虚拟段地址导致增加地址转换时间，因为 凝结。 本发明的地址分配机制通过以伪随机顺序分配虚拟分段地址来减少分组。 这降低了分配在一起的虚拟分段地址在地址转换表中的相同集合或虚拟分段地址集合的可能性。