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    Universal inter-layer interconnect for multi-layer semiconductor stacks
    1.
    发明授权
    Universal inter-layer interconnect for multi-layer semiconductor stacks 有权
    用于多层半导体堆叠的通用层间互连

    公开(公告)号：US08330489B2

    公开(公告)日：2012-12-11

    申请号：US12431259

    申请日：2009-04-28

    申请人： Gerald K. Bartley ,  Russell Dean Hoover ,  Charles Luther Johnson ,  Steven Paul VanderWiel ,  Patrick Ronald Varekamp

    发明人： Gerald K. Bartley ,  Russell Dean Hoover ,  Charles Luther Johnson ,  Steven Paul VanderWiel ,  Patrick Ronald Varekamp

    IPC分类号： H01L25/00

    CPC分类号： G06F17/5068 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01087 ,  H01L2224/05599 ,  H01L2224/05099

    摘要： A circuit arrangement and method utilize a universal, standardized inter-layer interconnect in a multi-layer semiconductor stack to facilitate interconnection and communication between functional units disposed on a stack of semiconductor dies. Each circuit layer in the multi-layer semiconductor stack is required to include an inter-layer interface region that is disposed at substantially the same topographic location such that when the semiconductor dies upon which such circuit layers are disposed are arranged together in a stack, electrical conductors disposed within each semiconductor die are aligned with one another to provide an inter-layer bus that is oriented vertically, or transversely, with respect to the individual circuit layers. Based upon a standardized placement of the inter-layer interface region in each circuit layer, and a standardized arrangement of electrical conductors associated with the inter-layer bus, each circuit layer may designed using a standardized template upon which the design features necessary to implement the inter-layer bus are already provided, thereby simplifying circuit layer design and the interconnection of functional units to the inter-layer bus. In addition, vertically-oriented supernodes may be defined within a semiconductor stack to provide multiple independently-operating nodes having functional units disposed in multiple circuit layers of the stack.

    摘要翻译： 电路布置和方法利用多层半导体堆叠中的通用的标准化层间互连，以便于布置在半导体管芯堆叠上的功能单元之间的互连和通信。 多层半导体堆叠中的每个电路层需要包括布置在基本上相同的地形位置处的层间界面区域，使得当将这样的电路层设置在其上的半导体管芯堆叠在一起时，电气 布置在每个半导体管芯内的导体彼此对准以提供相对于各个电路层垂直或横向取向的层间总线。 基于每个电路层中的层间界面区域的标准化布置以及与层间总线相关联的电导体的标准化布置，每个电路层可以使用标准化模板来设计，在该模板上设计实现 已经提供了层间总线，从而简化了电路层设计和功能单元与层间总线的互连。 此外，可以在半导体堆叠内定义垂直取向的超节点，以提供多个独立运行的节点，其具有布置在堆叠的多个电路层中的功能单元。

    SRAM that can be clocked on either clock phase
    3.
    发明授权
    SRAM that can be clocked on either clock phase 失效
    可以在任一时钟阶段对SRAM进行时钟控制

    公开(公告)号：US06260164B1

    公开(公告)日：2001-07-10

    申请号：US09127355

    申请日：1998-07-31

    申请人： Anthony Gus Aipperspach ,  Leland Leslie Day ,  Paul Allen Ganfield ,  Charles Luther Johnson

    发明人： Anthony Gus Aipperspach ,  Leland Leslie Day ,  Paul Allen Ganfield ,  Charles Luther Johnson

    IPC分类号： G01R3128

    CPC分类号： G11C11/417

    摘要： A functional unit, such as an SRAM, in a single clock chip design that contains a scan path can be clocked on either rising edge and falling edge of the clock. The functional unit includes a clock signal having two phases and a plurality of latches for scanning. Two scan latches are added outside the array of the functional unit. In one clock phase, the two scan latches form a latch pair which is connected to the array at Scan-in side. In the other clock phase, one scan latch is connected to the array at the Scan-in side, and the other scan latch is connected to the array at the Scan-out side. In scan/hold operations, a first control signal for the array which is clocked at the falling edge of the clock leads a second control signal for the array which is clocked at the rising edge of the clock. In ABIST/functional operations, the first control signal for the array which is clocked at the falling edge of the clock trails the second control signal for the array which is clocked at the rising edge of the clock.

    摘要翻译： 包含扫描路径的单个时钟芯片设计中的诸如SRAM的功能单元可以在时钟的上升沿和下降沿被计时。 功能单元包括具有两相的时钟信号和用于扫描的多个锁存器。 两个扫描锁存器被添加到功能单元的阵列之外。 在一个时钟相位中，两个扫描锁存器形成一个锁存器对，其在Scan-in侧连接到阵列。 在另一个时钟阶段，一个扫描锁存器连接到Scan-in侧的阵列，另一个扫描锁存器连接到Scan-out侧的阵列。 在扫描/保持操作中，在时钟的下降沿被计时的阵列的第一控制信号引出在时钟的上升沿被计时的阵列的第二控制信号。 在ABIST /功能操作中，在时钟下降沿时钟脉冲的阵列的第一个控制信号跟踪在时钟上升沿时钟脉冲的阵列的第二个控制信号。

    Universal Inter-Layer Interconnect for Multi-Layer Semiconductor Stacks
    6.
    发明申请
    Universal Inter-Layer Interconnect for Multi-Layer Semiconductor Stacks 有权
    多层半导体堆叠的通用层间互连

    公开(公告)号：US20100271071A1

    公开(公告)日：2010-10-28

    申请号：US12431259

    申请日：2009-04-28

    申请人： Gerald K. Bartley ,  Russell Dean Hoover ,  Charles Luther Johnson ,  Steven Paul VanderWiel ,  Patrick Ronald Varekamp

    发明人： Gerald K. Bartley ,  Russell Dean Hoover ,  Charles Luther Johnson ,  Steven Paul VanderWiel ,  Patrick Ronald Varekamp

    IPC分类号： H01L25/00 ,  G06F17/50

    CPC分类号： G06F17/5068 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01087 ,  H01L2224/05599 ,  H01L2224/05099

    摘要： A circuit arrangement and method utilize a universal, standardized inter-layer interconnect in a multi-layer semiconductor stack to facilitate interconnection and communication between functional units disposed on a stack of semiconductor dies. Each circuit layer in the multi-layer semiconductor stack is required to include an inter-layer interface region that is disposed at substantially the same topographic location such that when the semiconductor dies upon which such circuit layers are disposed are arranged together in a stack, electrical conductors disposed within each semiconductor die are aligned with one another to provide an inter-layer bus that is oriented vertically, or transversely, with respect to the individual circuit layers. Based upon a standardized placement of the inter-layer interface region in each circuit layer, and a standardized arrangement of electrical conductors associated with the inter-layer bus, each circuit layer may designed using a standardized template upon which the design features necessary to implement the inter-layer bus are already provided, thereby simplifying circuit layer design and the interconnection of functional units to the inter-layer bus. In addition, vertically-oriented supernodes may be defined within a semiconductor stack to provide multiple independently-operating nodes having functional units disposed in multiple circuit layers of the stack.

    摘要翻译： 电路布置和方法利用多层半导体堆叠中的通用的标准化层间互连，以便于布置在半导体管芯堆叠上的功能单元之间的互连和通信。 多层半导体堆叠中的每个电路层需要包括布置在基本上相同的地形位置处的层间界面区域，使得当将这样的电路层设置在其上的半导体管芯堆叠在一起时，电气 布置在每个半导体管芯内的导体彼此对准以提供相对于各个电路层垂直或横向取向的层间总线。 基于每个电路层中的层间界面区域的标准化布置以及与层间总线相关联的电导体的标准化布置，每个电路层可以使用标准化模板来设计，在该模板上设计实现 已经提供了层间总线，从而简化了电路层设计和功能单元与层间总线的互连。 此外，可以在半导体堆叠内定义垂直取向的超节点，以提供多个独立运行的节点，其具有布置在堆叠的多个电路层中的功能单元。

    Apparatus and method to change a processor clock frequency
    7.
    发明授权
    Apparatus and method to change a processor clock frequency 失效
    改变处理器时钟频率的装置和方法

    公开(公告)号：US5815694A

    公开(公告)日：1998-09-29

    申请号：US576172

    申请日：1995-12-21

    申请人： Paul Allen Ganfield ,  Charles Luther Johnson ,  James David Strom

    发明人： Paul Allen Ganfield ,  Charles Luther Johnson ,  James David Strom

    IPC分类号： G06F1/08

    CPC分类号： G06F1/08

    摘要： An apparatus and method for providing a variable frequency clock source is described wherein the frequency may be changed while maintaining the phase of the clock signal. A frequency conversation circuit, such as a phase locked loop (PLL), is employed to change the frequency of the clock and is controlled by a control unit which maintains the phase of the output clock signal while undergoing a frequency change operation.

    摘要翻译： 描述了一种用于提供可变频率时钟源的装置和方法，其中可以在保持时钟信号的相位的同时改变频率。 使用诸如锁相环（PLL）的频率对话电路来改变时钟的频率，并且由控制单元控制，该控制单元在经历频率改变操作时保持输出时钟信号的相位。

    Pipelined memory interface and method for using the same
    8.
    发明授权
    Pipelined memory interface and method for using the same 失效
    流水线存储器接口及其使用方法

    公开(公告)号：US5790838A

    公开(公告)日：1998-08-04

    申请号：US700263

    申请日：1996-08-20

    申请人： John David Irish ,  Charles Luther Johnson ,  David John Krolak ,  Sheldon Bernard Levenstein

    发明人： John David Irish ,  Charles Luther Johnson ,  David John Krolak ,  Sheldon Bernard Levenstein

    IPC分类号： G11C7/10 ,  G06F1/04

    CPC分类号： G11C7/1039 ,  G11C7/1072

    摘要： According to the present invention, a pipelined SRAM structure and clocking method is disclosed. The SRAM interface and clocking method are specifically intended for use with Level 2 and Level 3 cache SRAM memory devices. In the present invention, the oscillator that generates the clock signal for the CPU is also used to generate the clock signals for all of the other components that interface with the SRAM. Each of the generated clock signals are dependant on the same clock event, allowing the clock speed to be decreased for testing or debugging while maintaining higher speed clock edge relationships. The various clock signals that are generated from the oscillator are used to cycle-steal time from multiple cycles. This technique allows sub-5 nanosecond (nS) access to Level 2 and Level 3 cache memory devices that have access times greater than 5 nS.

    摘要翻译： 根据本发明，公开了流水线SRAM结构和计时方法。 SRAM接口和时钟方法专门用于2级和3级缓存SRAM存储器件。 在本发明中，生成用于CPU的时钟信号的振荡器也用于生成与SRAM接口的所有其它组件的时钟信号。 每个生成的时钟信号都取决于相同的时钟事件，允许降低时钟速度以进行测试或调试，同时保持更高速度的时钟边缘关系。 从振荡器产生的各种时钟信号用于从多个周期循环窃取时间。 这种技术允许5纳秒（nS）访问访问次数大于5 nS的2级和3级高速缓存存储器设备。