公开(公告)号：US12062397B2

公开(公告)日：2024-08-13

申请号：US17585261

申请日：2022-01-26

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Kha Nguyen ,  Hien Pham ,  Duc Nguyen

IPC: G11C16/16 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

CPC classification number: G11C16/16 ,  G11C16/102 ,  G11C16/26 ,  G11C16/30

Abstract: Numerous embodiments of a transceiver for providing high voltages for use during erase or program operations in a non-volatile memory system are disclosed. In one embodiment, a transceiver comprises a PMOS transistor and a native NMOS transistor. In another embodiment, a transceiver comprises a PMOS transistor, an NMOS transistor, and a native NMOS transistor.

公开(公告)号：US20240265951A1

公开(公告)日：2024-08-08

申请号：US18137370

申请日：2023-04-20

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Hoa Vu ,  Stephen Trinh ,  Stanley Hong ,  Thuan Vu ,  Nghia Le ,  Duc Nguyen ,  Hien Pham

IPC: G11C5/14 ,  G11C7/02 ,  G11C13/00

CPC classification number: G11C5/147 ,  G11C7/02 ,  G11C13/004

Abstract: In one example, a system comprises a current-to-voltage converter to generate differential voltages from differential currents comprising a first current and a second current, the current-to-voltage converter comprising: a first bitline to provide the first current; a second bitline to provide the second current; a first regulator to apply a first voltage to the first bitline; a second regulator to apply a second voltage to the second bitline; a regulating circuit comprising a first input terminal, a second input terminal, a first output terminal, and a second output terminal, the first output terminal and the second output terminal providing the differential voltages; and a common mode circuit.

公开(公告)号：US20230141943A1

公开(公告)日：2023-05-11

申请号：US17585261

申请日：2022-01-26

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Kha Nguyen ,  Hien Pham ,  Duc Nguyen

IPC: G11C16/16 ,  G11C16/10 ,  G11C16/30 ,  G11C16/26

CPC classification number: G11C16/16 ,  G11C16/102 ,  G11C16/30 ,  G11C16/26

Abstract: Numerous embodiments of a transceiver for providing high voltages for use during erase or program operations in a non-volatile memory system are disclosed. In one embodiment, a transceiver comprises a PMOS transistor and a native NMOS transistor. In another embodiment, a transceiver comprises a PMOS transistor, an NMOS transistor, and a native NMOS transistor.