公开(公告)号：US20250140601A1

公开(公告)日：2025-05-01

申请号：US18834746

申请日：2023-01-30

Applicant: Soitec

Inventor： Carine Duret ,  Ludovic Ecarnot ,  Charlene Porta

IPC: H01L21/762 ,  H01L21/324

Abstract: A method for fabricating a double semiconductor-on-insulator structure comprising the steps of: providing a first donor substrate and a handle substrate, forming a weakened zone in the donor substrate so as to delimit a first semiconductor layer to be transferred, bonding the first donor substrate to the handle substrate, a first electrically insulating layer being at the interface, and detaching at the weakened zone, treating the surface of the first transferred semiconductor layer comprising: a rapid thermal annealing, a thermal oxidation followed by a deoxidation, a smoothing heat treatment at a temperature of above 1000° C. in a non-oxidizing atmosphere, chemical-mechanical polishing, providing a second donor substrate of a second semiconductor layer to be transferred, transferring the second semiconductor layer, a second electrically insulating layer being at the interface.

公开(公告)号：US11205702B2

公开(公告)日：2021-12-21

申请号：US16086275

申请日：2017-03-31

Applicant: Soitec

Inventor： Christophe Figuet ,  Ludovic Ecarnot ,  Bich-Yen Nguyen ,  Walter Schwarzenbach ,  Daniel Delprat ,  Ionut Radu

IPC: H01L29/161 ,  H01L23/00 ,  H01L21/306

Abstract: A method for manufacturing a structure comprising a first substrate comprising at least one electronic component likely to be damaged by a temperature higher than 400° C. and a semiconductor layer extending on the first substrate comprises: (a) providing a first bonding metal layer on the first substrate, (b) providing a second substrate comprising successively: a semiconductor base substrate, a stack of a plurality of semiconductor epitaxial layers, a layer of SixGe1-x, with 0≤x≤1 being located at the surface of said stack opposite to the base substrate, and a second bonding metal layer, (c) bonding the first substrate and the second substrate through the first and second bonding metal layers at a temperature lower than or equal to 400° C., and (d) removing a part of the second substrate so as to transfer the layer of SixGe1-x on the first substrate using a selective etching process.

公开(公告)号：US11127624B2

公开(公告)日：2021-09-21

申请号：US16495362

申请日：2018-03-21

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Oleg Kononchuk ,  Ludovic Ecarnot

IPC: H01L21/762 ,  H01L27/146 ,  H01L31/028 ,  H01L21/02 ,  H01L21/203

Abstract: A semiconductor on insulator type structure, which may be used for a front side type imager, successively comprises, from its rear side to its front side, a semiconductor support substrate, an electrically insulating layer and an active layer comprising a monocrystalline semiconductor material. The active layer is made of a semiconductor material having a state of mechanical stress with respect to the support substrate, and the support substrate comprises, on its rear side, a silicon oxide layer, the thickness of the oxide layer being chosen to compensate bow induced by the mechanical stress between the active layer and the support substrate during cooling of the structure after the formation by epitaxy of at least a part of the active layer on the support substrate.

公开(公告)号：US20200328094A1

公开(公告)日：2020-10-15

申请号：US16305695

申请日：2017-05-24

Applicant: Soitec

Inventor： Bich-Yen Nguyen ,  Ludovic Ecarnot ,  Nadia Ben Mohamed ,  Christophe Malville

IPC: H01L21/56 ,  H01L21/48 ,  H01L21/78

Abstract: A method of forming a semiconductor structure includes introducing, at selected conditions, hydrogen and helium species (e.g., ions) in a temporary support to form a plane of weakness at a predetermined depth therein, and to define a superficial layer and a residual part of the temporary support; forming on the temporary support an interconnection layer; placing at least one semiconductor chip on the interconnection layer assembling a stiffener on a back side of the at least one semiconductor chip; and providing thermal energy to the temporary support to detach the residual part and provide the semiconductor structure. The interconnection layer forms an interposer free from any through via.

公开(公告)号：US10163682B2

公开(公告)日：2018-12-25

申请号：US15603830

申请日：2017-05-24

Applicant: Soitec

Inventor： Cédric Malaquin ,  Ludovic Ecarnot ,  Damien Parissi

IPC: H01L21/762 ,  H01L21/322 ,  H01L21/365 ,  H01L21/265 ,  H01L21/18

Abstract: The present disclosure relates to a process for the manufacture of a high resistivity semiconductor substrate, comprising the following stages: providing a first substrate with an in-depth weakened layer; providing a second substrate with a layer of an oxide at the surface; attaching the first substrate to the second substrate so as to form a compound substrate comprising a layer of buried oxide; and cleaving the compound substrate at the level of the weakened layer. The process additionally comprises at least one stage of stabilization, in particular, a stabilization heat treatment, of the second substrate with the layer of oxide before the stage of cleaving at the level of the weakened layer.

公开(公告)号：US20170345709A1

公开(公告)日：2017-11-30

申请号：US15603830

申请日：2017-05-24

Applicant: Soitec

Inventor： Cédric Malaquin ,  Ludovic Ecarnot ,  Damien Parissi

IPC: H01L21/762

CPC classification number: H01L21/76254 ,  H01L21/187 ,  H01L21/26506 ,  H01L21/3226 ,  H01L21/76251

Abstract: The present disclosure relates to a process for the manufacture of a high resistivity semiconductor substrate, comprising the following stages: providing a first substrate with an in-depth weakened layer; providing a second substrate with a layer of an oxide at the surface; attaching the first substrate to the second substrate so as to form a compound substrate comprising a layer of buried oxide; and cleaving the compound substrate at the level of the weakened layer. The process additionally comprises at least one stage of stabilization, in particular, a stabilization heat treatment, of the second substrate with the layer of oxide before the stage of cleaving at the level of the weakened layer.

公开(公告)号：US20250015122A1

公开(公告)日：2025-01-09

申请号：US18888578

申请日：2024-09-18

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Ludovic Ecarnot ,  Damien Massy ,  Nadia Ben Mohamed ,  Nicolas Daval ,  Christophe Girard ,  Christophe Maleville

IPC: H01L27/146 ,  H01L21/265 ,  H01L21/322 ,  H01L21/762 ,  H01L31/18

Abstract: A structure for a front-side image sensor comprises a semiconductor substrate, an electrically insulating layer overlying the semiconductor substrate, and an active layer overlying the electrically insulating layer. The semiconductor substrate comprises a trapping layer, the trapping layer including cavities therein. The structure further comprises a plurality of electrically isolating trenches extending vertically through the active layer to the electrically insulating layer. The plurality of electrically isolating trenches define a plurality of pixels. Also disclosed is a structure comprises a carrier substrate, an electrically insulating layer overlying the carrier substrate and a trapping layer, and a semiconductive layer overlying the electrically insulating layer. The trapping layer comprises cavities therein. The structure further comprises a plurality of electrically isolating trenches extending vertically through the semiconductive layer to the electrically insulating layer.

公开(公告)号：US20240145314A1

公开(公告)日：2024-05-02

申请号：US18402215

申请日：2024-01-02

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Ludovic Ecarnot ,  Nicolas Daval ,  Bich-Yen Nguyen ,  Guillaume Besnard

IPC: H01L21/8238 ,  H01L21/324 ,  H01L21/762

CPC classification number: H01L21/823821 ,  H01L21/3247 ,  H01L21/7624

Abstract: A method for manufacturing a CFET device comprises forming a substrate of the double semi-conductor on insulator type, successively comprising, from the base to the surface thereof: a carrier substrate, a first electrically insulating layer, a first single-crystal semiconductor layer, a second electrically insulating layer and a second single-crystal semiconductor layer. Slices are formed into the substrate to the first electrically insulating layer so as to form at least one fin (F). A channel of a first transistor is formed in the first semiconductor layer and a channel of a second transistor is formed opposite the first transistor in the second semiconductor layer. Formation of the substrate of the double semi-conductor on insulator type comprises: a first and a second step of transferring a layer and thermal processing at a temperature that is sufficiently high to smooth the first single-crystal semiconductor layer to a roughness lower than 0.1 nm RMS.

公开(公告)号：US20230230874A1

公开(公告)日：2023-07-20

申请号：US18007145

申请日：2021-06-23

Applicant: Soitec

Inventor： Bruno Clemenceau ,  Ludovic Ecarnot ,  Aymen Ghorbel ,  Marcel Broekaart ,  Daniel Delprat ,  Séverin Rouchier ,  Stephane Thieffry ,  Carine Duret

IPC: H01L21/762 ,  H01L21/683 ,  H01L21/02

CPC classification number: H01L21/76254 ,  H01L21/6835 ,  H01L21/02274

Abstract: A method for transferring a thin layer onto a carrier substrate comprises preparing a carrier substrate using a preparation method involving supplying a base substrate having, on a main face, a charge-trapping layer and forming a dielectric layer having a thickness greater than 200 nm on the charge-trapping layer. Once the dielectric layer is formed, the ionized deposition and sputtering of the dielectric layer are simultaneously performed. The transfer method also comprises assembling, by way of molecular adhesion and with an unpolished free face of the dielectric layer, a donor substrate to the dielectric layer of the carrier substrate, the donor substrate having an embrittlement plane defining the thin layer. Finally, the method comprises splitting the donor substrate at the embrittlement plane to release the thin layer and to transfer it onto the carrier substrate.

公开(公告)号：US20210384223A1

公开(公告)日：2021-12-09

申请号：US17254808

申请日：2019-06-21

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Manuel Sellier ,  Ludovic Ecarnot

IPC: H01L27/12 ,  H01L27/146

Abstract: The invention relates to a front-side imager comprising in succession: —a semiconductor carrier substrate, a first electrically insulating separating layer, and a single-crystal semiconductor layer, called the active layer, comprising a matrix array of photodiodes, wherein the imager further comprises between the carrier substrate and the first electrically insulating layer: —a second electrically insulating separating layer, and —a second semiconductor or electrically conductive layer, called the intermediate layer, arranged between the second separating layer and the first separating layer, the second separating layer being thicker than the first separating layer.