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    High speed bus with tree structure for selecting bus driver
    2.
    发明授权
    High speed bus with tree structure for selecting bus driver 失效
    具有树型结构的高速总线，用于选择公共汽车司机

    公开(公告)号：US5936424A

    公开(公告)日：1999-08-10

    申请号：US950380

    申请日：1997-10-14

    申请人： Steven P. Young ,  Kamal Chaudhary ,  Shekhar Bapat ,  Sridhar Krishnamurthy ,  Philip D. Costello

    发明人： Steven P. Young ,  Kamal Chaudhary ,  Shekhar Bapat ,  Sridhar Krishnamurthy ,  Philip D. Costello

    IPC分类号： H03K19/0175 ,  H03K19/173 ,  H03K19/0185 ,  H03K19/177

    CPC分类号： H03K19/1737 ,  H03K19/017581

    摘要： According to the invention, a structure is provided for driving a bus line that is both fast and small. Instead of a plurality of tristate buffers, one for each input signal, a plurality of multiplexers or gates is connected into a tree structure. The tristate enable line of the tristate buffer becomes the control line for enabling the tree structure to place its own input signal onto the bus instead of propagating the signal already on the bus. A buffer element then allows the resulting signal to be tapped from the bus. One embodiment of the invention includes lookahead logic similar to a lookahead carry chain. This allows large numbers of input lines to be connected to a bus line while retaining high speed. The symmetrical delay of a tree structure minimizes the greatest delay and thus increases predicted speed.

    摘要翻译： 根据本发明，提供一种用于驱动快速且小的总线的结构。 代替多个三态缓冲器，每个输入信号一个，多个多路复用器或门连接到树结构中。 三态缓冲器的三态使能线路成为控制线，用于使树结构能够将其自己的输入信号放置在总线上，而不是传播已经在总线上的信号。 然后，缓冲元件允许从总线中抽出所得到的信号。 本发明的一个实施例包括类似于前瞻携带链的前瞻逻辑。 这允许大量输入线连接到总线，同时保持高速。 树结构的对称延迟使最大延迟最小化，从而增加预测速度。

    High speed bidirectional bus with multiplexers
    3.
    发明授权
    High speed bidirectional bus with multiplexers 失效
    具有多路复用器的高速双向总线

    公开(公告)号：US5847580A

    公开(公告)日：1998-12-08

    申请号：US729065

    申请日：1996-10-10

    申请人： Shekhar Bapat ,  Sridhar Krishnamurthy

    发明人： Shekhar Bapat ,  Sridhar Krishnamurthy

    IPC分类号： H03K19/173 ,  H03K19/0175

    CPC分类号： H03K19/1737

    摘要： A multiplexer chain is coupled to two logic gates which in turn propagate their respective output signals in different directions, thereby providing bidirectional signal distribution. The output lines of multiple multiplexer chains are combined together using a logic gate chain to create a bus line with a larger number of drivers while substantially maintaining switching speed and flexibility in routability. In one embodiment, two OR chains propagate signals in opposite directions. The top OR chain combines the outputs of all the multiplexer chains to its left. Similarly, the bottom OR chain combines the outputs of all the multiplexer chains to its right. The output of the entire bus is provided at both the leftmost and the rightmost end of the OR chain. The bus output is also provided at tap points by combining the outputs of the top logic gate chain and the bottom logic gate chain using a logic gate. The top logic gate chain provides the outputs of all drivers to the left of the tap point while the bottom logic gate chain provides the outputs of all drivers to the right of the tap point.

    摘要翻译： 多路复用器链耦合到两个逻辑门，其又在不同方向上传播它们各自的输出信号，由此提供双向信号分配。 使用逻辑门链将多个多路复用器链的输出线组合在一起，以创建具有更多数量驱动器的总线，同时基本上保持了可切换的切换速度和灵活性。 在一个实施例中，两个OR链沿相反方向传播信号。 顶部OR链将所有多路复用器链的输出组合到其左侧。 类似地，底部OR链将所有多路复用器链的输出组合到其右侧。 整个总线的输出端设在OR链的最左端和最右端。 总线输出也通过使用逻辑门组合顶部逻辑门链和底部逻辑门链的输出而在抽头点处提供。 顶部逻辑门链提供所有驱动器在分接点左侧的输出，而底部逻辑门链提供所有驱动器在分接点右侧的输出。

    Configurable logic element with fast feedback paths
    4.
    发明授权
    Configurable logic element with fast feedback paths 失效
    具有快速反馈路径的可组态逻辑元件

    公开(公告)号：US5963050A

    公开(公告)日：1999-10-05

    申请号：US823265

    申请日：1997-03-24

    申请人： Steven P. Young ,  Bernard J. New ,  Nicolas John Camilleri ,  Trevor J. Bauer ,  Shekhar Bapat ,  Kamal Chaudhary ,  Sridhar Krishnamurthy

    发明人： Steven P. Young ,  Bernard J. New ,  Nicolas John Camilleri ,  Trevor J. Bauer ,  Shekhar Bapat ,  Kamal Chaudhary ,  Sridhar Krishnamurthy

    IPC分类号： H01L25/00 ,  H03K19/173 ,  H03K19/177

    CPC分类号： H03K19/1737 ,  H03K19/17704 ,  H03K19/17736 ,  H03K19/17796

    摘要： The invention provides an FPGA interconnect structure preferably included in an array of identical tiles. Each tile comprises a logic block that includes a Configurable Logic Element (CLE) and an output multiplexer. Fast feedback paths are provided within the logic block to connect the CLE outputs to the CLE inputs, either directly or through an input multiplexer. The fast feedback paths bypass the output multiplexer and therefore provide faster feedback than can be obtained in most conventional FPGA logic blocks. In one embodiment, the fast feedback paths provide the ability for all function generators in one CLE to drive each other through fast feedback paths, regardless of how logic is mapped into the function generators of the CLE.

    摘要翻译： 本发明提供了优选地包括在相同瓦片阵列中的FPGA互连结构。 每个瓦片包括包括可配置逻辑元件（CLE）和输出多路复用器的逻辑块。 在逻辑块内提供快速反馈路径，以将CLE输出直接或通过输入多路复用器连接到CLE输入。 快速反馈路径绕过输出多路复用器，因此提供比在大多数常规FPGA逻辑块中可以获得的更快的反馈。 在一个实施例中，快速反馈路径提供了一个CLE中的所有功能发生器通过快速反馈路径彼此驱动的能力，而不管逻辑如何映射到CLE的函数发生器中。

    Timing driven logic block configuration
    7.
    发明授权
    Timing driven logic block configuration 有权
    定时驱动逻辑块配置

    公开(公告)号：US07926016B1

    公开(公告)日：2011-04-12

    申请号：US12344155

    申请日：2008-12-24

    申请人： Priya Sundararajan ,  Sridhar Krishnamurthy

    发明人： Priya Sundararajan ,  Sridhar Krishnamurthy

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5054

    摘要： A method of configuring a logic block of a programmable logic device (PLD) during physical implementation of a circuit design, wherein ports of the logic block are selectively registered, can include identifying the logic block of the PLD, wherein the logic block is located on a critical path. For each of a plurality of selectively registerable portions of the logic block, the method can include computing input slacks and output slacks based upon potential register usage within the logic block. The method further can include determining register usage for the logic block by maximizing a function which depends upon a measure of worst case slack for pipeline stages.

    摘要翻译： 一种在电路设计的物理实现期间配置可编程逻辑器件（PLD）的逻辑块的方法，其中逻辑块的端口被选择性地注册，可以包括识别PLD的逻辑块，其中逻辑块位于 一个关键的路径。 对于逻辑块的多个可选择地可注册部分中的每一个，该方法可以包括基于逻辑块内的潜在寄存器使用计算输入宽度和输出宽度。 该方法还可以包括通过使取决于流水线级的最差情况松弛的度量的函数最大化来确定逻辑块的寄存器使用。

    Implementation of alternate solutions in technology mapping and placement
    8.
    发明授权
    Implementation of alternate solutions in technology mapping and placement 有权
    在技​​术测绘和放置中实施替代解决方案

    公开(公告)号：US07610573B1

    公开(公告)日：2009-10-27

    申请号：US11881307

    申请日：2007-07-26

    申请人： Vi Chi Chan ,  Tetse Jang ,  Sridhar Krishnamurthy ,  Kevin Chung

    发明人： Vi Chi Chan ,  Tetse Jang ,  Sridhar Krishnamurthy ,  Kevin Chung

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5054 ,  G06F2217/08

    摘要： A computer-implemented method of implementing a circuit design within a target integrated circuit (IC) can include, during technology mapping of the circuit design, determining a plurality of implementations of at least one sub-circuit of the circuit design and placing the circuit design on the target IC using a primary implementation of the plurality of implementations of the sub-circuit. The primary implementation of the sub-circuit can be selectively replaced with an alternate implementation of the sub-circuit selected from the plurality of implementations of the sub-circuit. The placed circuit design, including either the primary implementation or the alternate implementation of the sub-circuit, can be output.

    摘要翻译： 在目标集成电路（IC）中实现电路设计的计算机实现的方法可以包括在电路设计的技术映射期间，确定电路设计的至少一个子电路的多个实现并且将电路设计 在目标IC上使用子电路的多个实现的主要实现。 子电路的主要实现可以被选择性地替换为从子电路的多个实现中选择的子电路的替代实现。 可以输出放置的电路设计，包括子电路的主要实现或替代实现。

    Methods of generating test designs for testing specific routing resources in programmable logic devices
    9.
    发明授权
    Methods of generating test designs for testing specific routing resources in programmable logic devices 失效
    生成用于测试可编程逻辑器件中特定路由资源的测试设计的方法

    公开(公告)号：US07058919B1

    公开(公告)日：2006-06-06

    申请号：US10696357

    申请日：2003-10-28

    申请人： Jay T. Young ,  Sridhar Krishnamurthy ,  Jeffrey V. Lindholm ,  Ian L. McEwen

    发明人： Jay T. Young ,  Sridhar Krishnamurthy ,  Jeffrey V. Lindholm ,  Ian L. McEwen

    IPC分类号： G06F17/50

    CPC分类号： G01R31/318516 ,  G01R31/31704

    摘要： Methods of directly targeting specified routing resources in a PLD, e.g., routing resources that need to be tested. Test designs are produced that implement observable nets using the targeted routing resources. A PLD router is used to route from a target routing resource backwards through the routing fabric of the PLD to the source of an observable net. The net is identified based on the source, and loads of the net are identified as router load targets. The router is then used to route from the target routing resource forwards to one of the loads on the net. This process can be repeated for a list of target routing resources to provide a test design that tests as many of the targeted routing resources as possible. Additional test designs can be created to test remaining target routing resources. In other embodiments, the router routes first forwards, then backwards.

    摘要翻译： 直接针对PLD中的指定路由资源的方法，例如路由需要测试的资源。 使用目标路由资源实现可观察网络的测试设计。 PLD路由器用于从目标路由资源向后路由PLD的路由结构到可观察网络的源。 网络基于源标识，网络的负载被标识为路由器负载目标。 路由器然后用于从目标路由资源转发到网络上的一个负载。 可以针对目标路由资源列表重复此过程，以提供尽可能多的目标路由资源的测试设计。 可以创建其他测试设计来测试剩余的目标路由资源。 在其他实施例中，路由器首先向前路由，然后向后路由。

    Associative management of multimedia assets and associated resources using multi-domain agent-based communication between heterogeneous peers
    10.
    发明授权
    Associative management of multimedia assets and associated resources using multi-domain agent-based communication between heterogeneous peers 有权
    多媒体资产和相关资源的联合管理使用异构同层之间的多域代理进行通信

    公开(公告)号：US06574655B1

    公开(公告)日：2003-06-03

    申请号：US09342490

    申请日：1999-06-29

    申请人： Scott A. Libert ,  Robert J. Woolridge ,  Baochun Jin ,  Alex C. Tran ,  P. Murugavel ,  Mark S. Hillebrandt ,  Suhas Joshi ,  Sridhar Krishnamurthy ,  Rajagopal Govindakrishnan

    发明人： Scott A. Libert ,  Robert J. Woolridge ,  Baochun Jin ,  Alex C. Tran ,  P. Murugavel ,  Mark S. Hillebrandt ,  Suhas Joshi ,  Sridhar Krishnamurthy ,  Rajagopal Govindakrishnan

    IPC分类号： G06F1516

    CPC分类号： H04L67/104 ,  H04L29/06027 ,  H04L63/10 ,  H04L67/2819 ,  H04L67/2823 ,  H04L67/2828 ,  H04L69/24 ,  H04L69/329 ,  H04L2463/101 ,  Y10S707/99945

    摘要： Associative management of distributed multimedia assets and associated resources using multi-domain agent-based communication between heterogeneous peers is achieved using an Asset/Resource Management (ARM) platform architecture that has an ARM Framework that is used by Asset Management Agents. The ARM Framework includes an ARM Infrastructure which is a system of protocols and libraries from which communities of agents that are grouped in logical Agent Domains are built. The agents communicate via the KQML language embedded within TCP/IP messages, advertise their capabilities and cooperate together to perform meaningful work. An XML-based language is used to embed “content” within the KQML language, providing a self-describing data representation using various character sets. The ARM Framework includes system agents including in each Agent Domain a Resolver for keeping track of asset logical locations, an Agent Name Server (ANS) for keeping track of security access to the assets, and the “Yellow Pages” containing the Advertised System Knowledge (ASK) agent for keeping track of the capabilities of the Asset Management Agents.

    摘要翻译： 使用具有由资产管理代理使用的ARM框架的资产/资源管理（ARM）平台架构实现了使用异构对等体之间的基于多域代理的通信的分布式多媒体资产和相关资源的关联管理。 ARM框架包括一个ARM基础架构，它是一个协议和库的系统，构建了分组在逻辑代理域中的代理团体。 代理人通过嵌入在TCP / IP消息中的KQML语言进行通信，宣传他们的能力，并且携手合作，进行有意义的工作。 使用基于XML的语言将“内容”嵌入到KQML语言中，使用各种字符集提供自描述数据表示。 ARM框架包括系统代理，包括每个代理域中的一个用于跟踪资产逻辑位置的解析器，用于跟踪资产安全访问的代理名称服务器（ANS）和包含广告系统知识的“黄页”（ ASK）代理，用于跟踪资产管理代理的能力。