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    Configurable logic element with fast feedback paths
    2.
    发明授权
    Configurable logic element with fast feedback paths 失效
    具有快速反馈路径的可组态逻辑元件

    公开(公告)号：US5963050A

    公开(公告)日：1999-10-05

    申请号：US823265

    申请日：1997-03-24

    申请人： Steven P. Young ,  Bernard J. New ,  Nicolas John Camilleri ,  Trevor J. Bauer ,  Shekhar Bapat ,  Kamal Chaudhary ,  Sridhar Krishnamurthy

    发明人： Steven P. Young ,  Bernard J. New ,  Nicolas John Camilleri ,  Trevor J. Bauer ,  Shekhar Bapat ,  Kamal Chaudhary ,  Sridhar Krishnamurthy

    IPC分类号： H01L25/00 ,  H03K19/173 ,  H03K19/177

    CPC分类号： H03K19/1737 ,  H03K19/17704 ,  H03K19/17736 ,  H03K19/17796

    摘要： The invention provides an FPGA interconnect structure preferably included in an array of identical tiles. Each tile comprises a logic block that includes a Configurable Logic Element (CLE) and an output multiplexer. Fast feedback paths are provided within the logic block to connect the CLE outputs to the CLE inputs, either directly or through an input multiplexer. The fast feedback paths bypass the output multiplexer and therefore provide faster feedback than can be obtained in most conventional FPGA logic blocks. In one embodiment, the fast feedback paths provide the ability for all function generators in one CLE to drive each other through fast feedback paths, regardless of how logic is mapped into the function generators of the CLE.

    摘要翻译： 本发明提供了优选地包括在相同瓦片阵列中的FPGA互连结构。 每个瓦片包括包括可配置逻辑元件（CLE）和输出多路复用器的逻辑块。 在逻辑块内提供快速反馈路径，以将CLE输出直接或通过输入多路复用器连接到CLE输入。 快速反馈路径绕过输出多路复用器，因此提供比在大多数常规FPGA逻辑块中可以获得的更快的反馈。 在一个实施例中，快速反馈路径提供了一个CLE中的所有功能发生器通过快速反馈路径彼此驱动的能力，而不管逻辑如何映射到CLE的函数发生器中。

    Multiplexer for implementing logic functions in a programmable logic device
    3.
    发明授权
    Multiplexer for implementing logic functions in a programmable logic device 有权
    用于在可编程逻辑器件中实现逻辑功能的多路复用器

    公开(公告)号：US06362648B1

    公开(公告)日：2002-03-26

    申请号：US09712038

    申请日：2000-11-13

    申请人： Bernard J. New ,  Steven P. Young ,  Shekhar Bapat ,  Kamal Chaudhary ,  Trevor J. Bauer ,  Roman Iwanczuk

    发明人： Bernard J. New ,  Steven P. Young ,  Shekhar Bapat ,  Kamal Chaudhary ,  Trevor J. Bauer ,  Roman Iwanczuk

    IPC分类号： G06F738

    CPC分类号： H03K19/17736 ,  H03K19/1737 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/1778

    摘要： The invention allows the implementation of common wide logic functions using only two function generators of a field programmable gate array. One embodiment of the invention provides a structure for implementing a wide AND-gate in an FPGA configurable logic element (CLE) or portion thereof that includes no more than two function generators. First and second function generators are configured as AND-gates, the output signals (first and second AND signals) being combined in a 2-to-1 multiplexer controlled by the first AND signal, “0” selecting the first AND signal and “1” selecting the second AND signal. Therefore, a wide AND-gate is provided having a number of input signals equal to the total number of input signals for the two function generators. In another embodiment, a wide OR-gate is provided by configuring the function generators as OR-gates and controlling the multiplexer using the second OR signal.

    摘要翻译： 本发明允许仅使用现场可编程门阵列的两个函数发生器实现普通的宽逻辑功能。 本发明的一个实施例提供了一种用于在FPGA可配置逻辑元件（CLE）或其部分中实现宽的与门的结构，其包括不超过两个功能发生器。 第一和第二功能发生器被配置为与门，输出信号（第一和第二AND信号）被组合在由第一AND信号控制的2对1多路复用器中，选择第一AND信号为“0”和“1” “选择第二个AND信号。 因此，提供了具有等于两个功能发生器的输入信号的总数的多个输入信号的宽AND门。 在另一个实施例中，通过将功能发生器配置为OR门并使用第二OR信号来控制多路复用器来提供宽的或门。

    Wide logic gate implemented in an FPGA configurable logic element
    4.
    发明授权
    Wide logic gate implemented in an FPGA configurable logic element 有权
    宽逻辑门在FPGA可配置逻辑元件中实现

    公开(公告)号：US06201410B1

    公开(公告)日：2001-03-13

    申请号：US09374470

    申请日：1999-08-13

    申请人： Bernard J. New ,  Steven P. Young ,  Shekhar Bapat ,  Kamal Chaudhary ,  Trevor J. Bauer ,  Roman Iwanczuk

    发明人： Bernard J. New ,  Steven P. Young ,  Shekhar Bapat ,  Kamal Chaudhary ,  Trevor J. Bauer ,  Roman Iwanczuk

    IPC分类号： H01L2500

    CPC分类号： H03K19/17736 ,  H03K19/1737 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/1778

    摘要： The invention allows the implementation of common wide logic functions using only two function generators of a field programmable gate array. One embodiment of the invention provides a structure for implementing a wide AND-gate in an FPGA configurable logic element (CLE) or portion thereof that includes no more than two function generators. First and second function generators are configured as AND-gates, the output signals (first and second AND signals) being combined in a 2-to-1 multiplexer controlled by the first AND signal, “0” selecting the first AND signal and “1” selecting the second AND signal. Therefore, a wide AND-gate is provided having a number of input signals equal to the total number of input signals for the two function generators. In another embodiment, a wide OR-gate is provided by configuring the function generators as OR-gates and controlling the multiplexer using the second OR signal.

    摘要翻译： 本发明允许仅使用现场可编程门阵列的两个函数发生器实现普通的宽逻辑功能。 本发明的一个实施例提供了一种用于在FPGA可配置逻辑元件（CLE）或其部分中实现宽的与门的结构，其包括不超过两个功能发生器。 第一和第二功能发生器被配置为与门，输出信号（第一和第二AND信号）被组合在由第一AND信号控制的2对1多路复用器中，选择第一AND信号为“0”和“1” “选择第二个AND信号。 因此，提供了具有等于两个功能发生器的输入信号的总数的多个输入信号的宽AND门。 在另一个实施例中，通过将功能发生器配置为OR门并使用第二OR信号来控制多路复用器来提供宽的或门。

    Programmable power reduction in a clock-distribution circuit
    5.
    发明授权
    Programmable power reduction in a clock-distribution circuit 失效
    时钟分配电路中的可编程功耗降低

    公开(公告)号：US6072348A

    公开(公告)日：2000-06-06

    申请号：US890952

    申请日：1997-07-09

    申请人： Bernard J. New ,  Trevor J. Bauer ,  Steven P. Young

    发明人： Bernard J. New ,  Trevor J. Bauer ,  Steven P. Young

    IPC分类号： G06F1/08 ,  G06F1/32 ,  H03K1/04

    CPC分类号： G06F1/32 ,  G06F1/08

    摘要： A clock distribution circuit and method for programmable ICs whereby the incoming clock frequency is optionally divided by two and distributed at the new, lower frequency. Programmable dual-edge/single-edge flip-flops are provided that optionally operate at twice the frequency of the distributed clock, being responsive to both rising and falling edges of the distributed clock. When the clock divider is enabled and the flip-flops are programmed as dual-edge, the operating frequency is the same as that of the incoming clock; however, the frequency of the distributed clock is reduced by one-half. This reduction halves the frequency at which the clock distribution circuits operate, and consequently approximately halves the power dissipated by the clock distribution circuit, thereby providing a programmable power-saving mode.

    摘要翻译： 一种用于可编程IC的时钟分配电路和方法，其中输入时钟频率可选地被二分频并以新的较低频率分布。 提供了可编程双边沿/单边沿触发器，可选地以分布式时钟频率的两倍工作，响应于分布式时钟的上升沿和下降沿。 当时钟分频器使能并且触发器被编程为双边沿时，工作频率与输入时钟的工作频率相同; 然而，分布式时钟的频率减少了一半。 这种减少将时钟分配电路工作的频率减半，从而将时钟分配电路消耗的功率大致减半，从而提供可编程省电模式。

    Applications of cascading DSP slices
    6.
    发明授权
    Applications of cascading DSP slices 有权
    级联DSP片的应用

    公开(公告)号：US07567997B2

    公开(公告)日：2009-07-28

    申请号：US11019518

    申请日：2004-12-21

    申请人： James M. Simkins ,  Steven P. Young ,  Jennifer Wong ,  Bernard J. New ,  Alvin Y. Ching

    发明人： James M. Simkins ,  Steven P. Young ,  Jennifer Wong ,  Bernard J. New ,  Alvin Y. Ching

    IPC分类号： G06F7/48

    CPC分类号： G06F7/5443

    摘要： In one embodiment an IC is disclosed which includes a plurality of cascaded digital signal processing slices, wherein each slice has a multiplier coupled to an adder via a multiplexer and each slice has a direct connection to an adjoining slice; and means for configuring the plurality of digital signal processing slices to perform one or more mathematical operations, via, for example, opmodes. This IC allows for the implementation of some basic math functions, such as add, subtract, multiply and divide. Many other applications may be implemented using the one or more DSP slices, for example, accumulate, multiply accumulate (MACC), a wide multiplexer, barrel shifter, counter, and folded, decimating, and interpolating FIRs to name a few.

    摘要翻译： 在一个实施例中，公开了一种IC，其包括多个级联的数字信号处理片，其中每个片具有经由多路复用器耦合到加法器的乘法器，并且每个片与直接连接到相邻片; 以及用于通过例如opmode来配置多个数字信号处理片以执行一个或多个数学运算的装置。 该IC允许实现一些基本的数学函数，例如加，减，乘和除。 可以使用一个或多个DSP片段来实现许多其它应用，例如，累加，乘法累加（MACC），宽多路复用器，桶形移位器，计数器和折叠，抽取和内插FIR等等。