公开(公告)号：US06469933B2

公开(公告)日：2002-10-22

申请号：US09952628

申请日：2001-09-13

申请人： Sun-Mi Choi ,  Yeong-Taek Lee ,  Young-Ho Lim

发明人： Sun-Mi Choi ,  Yeong-Taek Lee ,  Young-Ho Lim

IPC分类号： G11C1604

CPC分类号： G11C16/3427 ,  G11C16/10 ,  G11C16/12

摘要： Disclosed is a method for programming a non-volatile semiconductor memory device that avoids the program disturb problem. In the programming method, ground voltage is applied to a first bit line corresponding to a memory cell to be programmed, and power supply voltage is applied to a second bit line corresponding to a memory cell to be prevented from being programmed. Next, a program voltage is applied to a word line connected to the memory cell to be programmed. The program voltage is stepped up to a desired voltage level of each program cycle from the first voltage thereby to reduce coupling between selected and non-selected bit and word lines.

摘要翻译： 公开了一种用于编程避免程序干扰问题的非易失性半导体存储器件的方法。 在编程方法中，将接地电压施加到与待编程的存储单元相对应的第一位线，并且将电源电压施加到对应于存储器单元的第二位线以防止被编程。 接下来，将编程电压施加到连接到要编程的存储器单元的字线。 编程电压从第一电压升高到每个编程周期的期望电压电平，从而减少选定位和未选择位和字线之间的耦合。

公开(公告)号：US06611460B2

公开(公告)日：2003-08-26

申请号：US10131424

申请日：2002-04-22

申请人： Yeong-Taek Lee ,  Young-Ho Lim

发明人： Yeong-Taek Lee ,  Young-Ho Lim

IPC分类号： G11C1604

CPC分类号： G11C16/12 ,  G11C16/0483

摘要： A nonvolatile semiconductor memory device of the present invention has a well voltage detecting circuit. The well voltage detecting circuit detects whether a pocket p-type well voltage is equal to or is lower than a detection voltage (e.g., 0.1V) and outputs a detection signal at a high or low level. When the pocket p-type well voltage is identical to or lower than the detection voltage, a word line select signal generating circuit generates row select signals of respective rows in response to the detection signal. With this device, in case a well voltage of the pocket p-type well is increased due to applying a voltage into an unselected bit line, program and pass voltages are supplied to word lines at a point of time when the increased well voltage becomes lower than the detection voltage of the well voltage detecting circuit.

公开(公告)号：US20120307560A1

公开(公告)日：2012-12-06

申请号：US13465246

申请日：2012-05-07

申请人： Sung-Soo Lee ,  Young-Ho Lim ,  Hyun-Chul Cho ,  Dong-Hyuk Chae

发明人： Sung-Soo Lee ,  Young-Ho Lim ,  Hyun-Chul Cho ,  Dong-Hyuk Chae

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/26

摘要： A non-volatile memory device includes a memory cell array which includes a plurality of non-volatile memory cells, a plurality of word lines, and a plurality of bit lines. The memory device further includes an internal data output line for outputting data read from the bit lines of the memory array, and a page buffer operatively connected between a bit line of the memory cell array and the internal data output line. The page buffer includes a sense node which is selectively connected to the bit line, a latch circuit having a latch node which is selectively connected to the sense node, a latch input path which sets a logic voltage of the latch node in the programming mode and the read mode, and a latch output path which is separate from the latch input path.

摘要翻译： 非易失性存储器件包括存储单元阵列，其包括多个非易失性存储器单元，多个字线和多个位线。 存储器件还包括用于输出从存储器阵列的位线读取的数据的内部数据输出线以及可操作地连接在存储单元阵列的位线和内部数据输出线之间的页缓冲器。 页面缓冲器包括选择性地连接到位线的感测节点，具有选择性地连接到感测节点的锁存节点的锁存电路，将锁存节点的逻辑电压设置为编程模式的锁存器输入路径，以及 读取模式和与锁存器输入路径分离的锁存器输出路径。

公开(公告)号：US08174888B2

公开(公告)日：2012-05-08

申请号：US12752213

申请日：2010-04-01

申请人： Sung-Soo Lee ,  Young-Ho Lim ,  Hyun-Chul Cho ,  Dong-Hyuk Chae

发明人： Sung-Soo Lee ,  Young-Ho Lim ,  Hyun-Chul Cho ,  Dong-Hyuk Chae

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C16/26

摘要： In one aspect, a non-volatile memory device is provided which is operable in a programming mode and a read mode. The memory device includes a memory cell array which includes a plurality of non-volatile memory cells, a plurality of word lines, and a plurality of bit lines. The memory device further includes an internal data output line for outputting data read from the bit lines of the memory array, and a page buffer operatively connected between a bit line of the memory cell array and the internal data output line. The page buffer includes a sense node which is selectively connected to the bit line, a latch circuit having a latch node which is selectively connected to the sense node, a latch input path which sets a logic voltage of the latch node in the programming mode and the read mode, and a latch output path which is separate from the latch input path and which sets as logic voltage of the internal date output line according to the logic voltage of the latch node.

摘要翻译： 在一个方面，提供一种可在编程模式和读取模式下操作的非易失性存储器件。 存储器件包括存储单元阵列，其包括多个非易失性存储器单元，多个字线和多个位线。 存储器件还包括用于输出从存储器阵列的位线读取的数据的内部数据输出线以及可操作地连接在存储单元阵列的位线和内部数据输出线之间的页缓冲器。 页面缓冲器包括选择性地连接到位线的感测节点，具有选择性地连接到感测节点的锁存节点的锁存电路，将锁存节点的逻辑电压设置为编程模式的锁存器输入路径，以及 读取模式和与锁存器输入路径分离并根据锁存节点的逻辑电压设置为内部日期输出线的逻辑电压的锁存器输出路径。

公开(公告)号：US07864582B2

公开(公告)日：2011-01-04

申请号：US12191434

申请日：2008-08-14

申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Young-Ho Lim ,  Kang-Deog Suh

发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Young-Ho Lim ,  Kang-Deog Suh

IPC分类号： G11C16/06

CPC分类号： G11C16/0483 ,  G11C16/16

摘要： Methods of operating a charge trap nonvolatile memory device include operations to erase a first string of nonvolatile memory cells by selectively erasing a first plurality of nonvolatile memory cells in the first string and then selectively erasing a second plurality of nonvolatile memory cells in the first string, which may be interleaved with the first plurality of nonvolatile memory cells. This operation to selectively erase the first plurality of nonvolatile memory cells may include erasing the first plurality of nonvolatile memory cells while simultaneously biasing the second plurality of nonvolatile memory cells in a blocking condition that inhibits erasure of the second plurality of nonvolatile memory cells. The operation to selectively erase the second plurality of nonvolatile memory cells may include erasing the second plurality of nonvolatile memory cells while simultaneously biasing the first plurality of nonvolatile memory cells in a blocking condition that inhibits erasure of the first plurality of nonvolatile memory cells.

摘要翻译： 操作电荷阱非易失性存储装置的方法包括通过选择性地擦除第一串中的第一多个非易失性存储单元，然后选择性地擦除第一串中的第二多个非易失性存储单元来擦除第一串非易失性存储单元的操作， 其可以与第一多个非易失性存储器单元交错。 选择性地擦除第一多个非易失性存储单元的操作可以包括擦除第一多个非易失性存储单元，同时在禁止擦除第二多个非易失性存储单元的阻塞条件下同时偏置第二多个非易失性存储单元。 选择性地擦除第二多个非易失性存储单元的操作可以包括擦除第二多个非易失性存储单元，同时在禁止擦除第一多个非易失性存储单元的阻塞条件下同时偏置第一多个非易失性存储单元。

公开(公告)号：US07839691B2

公开(公告)日：2010-11-23

申请号：US12571980

申请日：2009-10-01

申请人： Dong-Hyuk Chae ,  Young-Ho Lim

发明人： Dong-Hyuk Chae ,  Young-Ho Lim

IPC分类号： G11C11/34

CPC分类号： G11C8/08 ,  G11C16/349

摘要： A non-volatile semiconductor memory device includes: cell strings connected to respective bit lines; each of the cell strings having a string select transistor connected to a string select line, a ground select transistor connected to a ground select line, and memory cells connected to corresponding word lines and connected in series between the string select transistor and the ground select transistor; a first voltage drop circuit configured to reduce an applied read voltage during a read operation; a second voltage drop circuit configured to reduce the applied read voltage; a string select line driver circuit configured to drive the string select line with the reduced voltage provided by the first voltage drop circuit; and a ground select line driver circuit configured to drive a ground select line with the reduced voltage provided by the second voltage drop circuit.

摘要翻译： 非易失性半导体存储器件包括：连接到相应位线的单元串; 每个单元串具有连接到串选择线的串选择晶体管，连接到接地选择线的接地选择晶体管和连接到对应字线并且串联连接在串选择晶体管和接地选择晶体管之间的存储单元 ; 第一电压降电路，被配置为在读取操作期间减小施加的读取电压; 配置为减小所施加的读取电压的第二电压降电路; 串行选择线驱动电路，被配置为利用由第一压降电路提供的降低的电压驱动串选择线; 以及接地选择线驱动电路，被配置为用由第二压降电路提供的降低的电压来驱动接地选择线。

公开(公告)号：US20100259982A1

公开(公告)日：2010-10-14

申请号：US12822246

申请日：2010-06-24

申请人： Dae-Seok Byeon ,  Young-Ho Lim

发明人： Dae-Seok Byeon ,  Young-Ho Lim

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C16/10 ,  G11C8/10 ,  G11C8/12 ,  G11C29/806 ,  G11C29/844

摘要： A flash memory device includes multiple memory blocks, a decoder configured to select at least one of the memory blocks in response to block select signals, a controller configured to generate the block select signals in response to a block address and to generate a flag signal when the block address corresponds to a bad block, and an output buffer configured to output fixed data in response to the flag signal indicating that the block address corresponds to the bad block. When the block address corresponds to a bad block, the controller generates the block select signals to cause the decoder to interrupt selection of a memory block corresponding to the block address.

摘要翻译： 闪速存储器件包括多个存储器块，被配置为响应于块选择信号来选择至少一个存储器块的解码器，被配置为响应于块地址产生块选择信号并且产生标志信号的控制器， 块地址对应于坏块，并且输出缓冲器被配置为响应于指示块地址对应于坏块的标志信号输出固定数据。 当块地址对应于坏块时，控制器产生块选择信号以使解码器中断对应于块地址的存储块的选择。

公开(公告)号：US07738298B2

公开(公告)日：2010-06-15

申请号：US12102262

申请日：2008-04-14

申请人： Dong-Hyuk Chae ,  Young-Ho Lim

发明人： Dong-Hyuk Chae ,  Young-Ho Lim

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/12 ,  G11C16/344 ,  G11C16/3445

摘要： A NAND flash memory device includes a high voltage switch and a bulk voltage supplying circuit. The high voltage switch is configured to transfer a word line voltage to selected word lines of selected memory cells. The bulk voltage supplying circuit is configured to provide a negative voltage to a bulk region of the high voltage switch in response to an operation mode.

摘要翻译： NAND闪速存储器件包括高压开关和体电压供应电路。 高电压开关被配置为将字线电压传送到所选存储单元的选定字线。 体电压供给电路被配置为响应于操作模式向高电压开关的体区提供负电压。

公开(公告)号：US07734880B2

公开(公告)日：2010-06-08

申请号：US11595925

申请日：2006-11-13

申请人： Sang-gu Kang ,  Young-Ho Lim

发明人： Sang-gu Kang ,  Young-Ho Lim

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/3454 ,  G11C16/3459

摘要： A memory system includes a flash memory and a memory controller configured to control the flash memory. The memory controller determines whether program data provided from a host are all stored in the flash memory during a program operation. When the determination result is that the program data are all stored in the flash memory, the memory controller controls the flash memory to execute a dummy program operation for the next wordline of a final wordline in which the program data are stored.

摘要翻译： 存储器系统包括闪速存储器和被配置为控制闪速存储器的存储器控​​制器。 存储器控制器在程序操作期间确定从主机提供的程序数据是否全部存储在闪速存储器中。 当确定结果是程序数据全部存储在闪速存储器中时，存储器控制器控制闪存以对存储程序数据的最终字线的下一个字线执行虚拟程序操作。

公开(公告)号：US07539063B2

公开(公告)日：2009-05-26

申请号：US11651521

申请日：2007-01-10

申请人： Sang-Gu Kang ,  Young-Ho Lim

发明人： Sang-Gu Kang ,  Young-Ho Lim

IPC分类号： G11C11/34

CPC分类号： G11C11/5628

摘要： Flash memory devices and methods of programming the same are provided. The flash memory devices include a plurality of memory cells storing multi-bit data representing at least one of first through fourth states and including most significant bits and least significant bits. The method includes programming the plural memory cells into a provisional state according to the least significant bit, and programming the plurality of memory cells into the second through fourth states from the first and provisional states according to the most significant bit. Programming the plurality of memory cells into the second through fourth states includes simultaneously programming the plurality of memory cells at least partially into at least two states during one programming operation period.

摘要翻译： 提供闪存设备及其编程方法。 闪速存储器件包括存储多位数据的多个存储单元，该多位数据表示第一至第四状态中的至少一个，并且包括最高有效位和最低有效位。 该方法包括根据最低有效位将多个存储器单元编程为临时状态，并根据最高有效位将第一至暂态状态的多个存储单元编程为第二至第四状态。 将多个存储器单元编程为第二至第四状态包括在一个编程操作周期期间至少部分地将多个存储器单元编程为至少两个状态。