公开(公告)号：US06469933B2

公开(公告)日：2002-10-22

申请号：US09952628

申请日：2001-09-13

申请人： Sun-Mi Choi ,  Yeong-Taek Lee ,  Young-Ho Lim

发明人： Sun-Mi Choi ,  Yeong-Taek Lee ,  Young-Ho Lim

IPC分类号： G11C1604

CPC分类号： G11C16/3427 ,  G11C16/10 ,  G11C16/12

摘要： Disclosed is a method for programming a non-volatile semiconductor memory device that avoids the program disturb problem. In the programming method, ground voltage is applied to a first bit line corresponding to a memory cell to be programmed, and power supply voltage is applied to a second bit line corresponding to a memory cell to be prevented from being programmed. Next, a program voltage is applied to a word line connected to the memory cell to be programmed. The program voltage is stepped up to a desired voltage level of each program cycle from the first voltage thereby to reduce coupling between selected and non-selected bit and word lines.

摘要翻译： 公开了一种用于编程避免程序干扰问题的非易失性半导体存储器件的方法。 在编程方法中，将接地电压施加到与待编程的存储单元相对应的第一位线，并且将电源电压施加到对应于存储器单元的第二位线以防止被编程。 接下来，将编程电压施加到连接到要编程的存储器单元的字线。 编程电压从第一电压升高到每个编程周期的期望电压电平，从而减少选定位和未选择位和字线之间的耦合。

公开(公告)号：US06594178B2

公开(公告)日：2003-07-15

申请号：US09872366

申请日：2001-05-31

申请人： Sun-Mi Choi ,  Yeong-Taek Lee

发明人： Sun-Mi Choi ,  Yeong-Taek Lee

IPC分类号： G11C1604

CPC分类号： G11C16/3409 ,  G11C16/0483 ,  G11C16/30 ,  G11C16/3404

摘要： A method is operable in a non-volatile memory device of a type having a plurality of blocks formed of a plurality of memory strings in which a plurality of memory cells are connected in series in which a programming operation is conducted after erasing memory cells. The method essentially including the steps of: erasing data held in the memory cells in a unit of the block; and applying a soft program voltage to word lines coupled with the erased memory cells in the unit of the block. The method improves a threshold voltage profile after an erasing cycle, whereby program stress can be minimized in a follow-up program operation.

摘要翻译： 一种方法可操作在具有由多个存储器串形成的多个块的类型的非易失性存储器件中，其中多个存储器单元串联连接，其中在擦除存储器单元之后进行编程操作。 该方法基本上包括以下步骤：以块为单位擦除保存在存储单元中的数据; 以及将软编程电压施加到以块为单位与擦除的存储器单元耦合的字线。 该方法改善了擦除周期之后的阈值电压分布，从而可以在后续程序操作中使程序应力最小化。

公开(公告)号：US06735116B2

公开(公告)日：2004-05-11

申请号：US10322268

申请日：2002-12-17

申请人： Yeong-Taek Lee ,  Young-ho Lim

发明人： Yeong-Taek Lee ,  Young-ho Lim

IPC分类号： G11C1604

CPC分类号： G11C16/08 ,  G11C8/12 ,  G11C2216/14

摘要： A NAND-type flash memory device includes a plurality of row selectors each corresponding to memory blocks of each mat therein. Each of the row selectors selects a corresponding memory block in response to block selection information. A decoding circuit and a register are supplied to each of the row selectors. The decoding circuit generates a block selection signal in response to the block selection information, and the register stores an output of the decoding circuit when a latch signal of a corresponding mat is activated. According to the above row selection construction, all mats or a part of memory blocks can be selected at the same time.

摘要翻译： NAND型闪速存储器件包括多个行选择器，每个行选择器对应于其中每个垫的存储块。 每个行选择器响应于块选择信息选择相应的存储器块。 解码电路和寄存器被提供给每个行选择器。 解码电路响应于块选择信息产生块选择信号，并且当对应的片的锁存信号被激活时，寄存器存储解码电路的输出。 根据上述行选择结构，可以同时选择所有的垫或一部分存储块。

公开(公告)号：US06611460B2

公开(公告)日：2003-08-26

申请号：US10131424

申请日：2002-04-22

申请人： Yeong-Taek Lee ,  Young-Ho Lim

发明人： Yeong-Taek Lee ,  Young-Ho Lim

IPC分类号： G11C1604

CPC分类号： G11C16/12 ,  G11C16/0483

摘要： A nonvolatile semiconductor memory device of the present invention has a well voltage detecting circuit. The well voltage detecting circuit detects whether a pocket p-type well voltage is equal to or is lower than a detection voltage (e.g., 0.1V) and outputs a detection signal at a high or low level. When the pocket p-type well voltage is identical to or lower than the detection voltage, a word line select signal generating circuit generates row select signals of respective rows in response to the detection signal. With this device, in case a well voltage of the pocket p-type well is increased due to applying a voltage into an unselected bit line, program and pass voltages are supplied to word lines at a point of time when the increased well voltage becomes lower than the detection voltage of the well voltage detecting circuit.

公开(公告)号：US09406359B2

公开(公告)日：2016-08-02

申请号：US14683186

申请日：2015-04-10

申请人： Hyun-Kook Park ,  Yeong-Taek Lee ,  Dae-Seok Byeon ,  Chi-Weon Yoon

发明人： Hyun-Kook Park ,  Yeong-Taek Lee ,  Dae-Seok Byeon ,  Chi-Weon Yoon

IPC分类号： G11C29/52 ,  G11C7/22 ,  G06F11/07 ,  G11C7/06 ,  G11C7/10 ,  G11C7/14 ,  G11C11/56 ,  G11C13/00 ,  G11C29/02 ,  G11C29/42 ,  G11C7/12

CPC分类号： G11C7/22 ,  G06F11/073 ,  G06F11/076 ,  G11C7/062 ,  G11C7/067 ,  G11C7/1045 ,  G11C7/12 ,  G11C7/14 ,  G11C11/5642 ,  G11C13/004 ,  G11C29/021 ,  G11C29/026 ,  G11C29/028 ,  G11C29/42 ,  G11C29/52 ,  G11C2013/0054 ,  G11C2213/72

摘要： A method of operating a memory system including memory cells commonly connected to a first signal line in a memory cell array includes; dividing the memory cells according to cell regions, and independently performing read operations on memory cells disposed in each cell region using a read reference selected from a plurality of read references and respectively corresponding to each cell region.

摘要翻译： 一种操作存储器系统的方法，包括：存储单元阵列中包含共同连接到第一信号线的存储单元; 根据单元区域划分存储单元，并且使用从多个读取参考中选择并且分别对应于每个单元区域的读取参考，独立地对设置在每个单元区域中的存储单元执行读取操作。

公开(公告)号：US08711610B2

公开(公告)日：2014-04-29

申请号：US13289277

申请日：2011-11-04

申请人： Hui-Kwon Seo ,  Yeong-Taek Lee ,  Yong-Shik Shin

发明人： Hui-Kwon Seo ,  Yeong-Taek Lee ,  Yong-Shik Shin

IPC分类号： G11C11/00

CPC分类号： G11C13/0004 ,  G11C13/004 ,  G11C13/0069

摘要： A non-volatile memory device, non-volatile memory cell array and related method of operation are disclosed. The non-volatile memory cell array includes a defined data unit stored in a plurality of non-volatile memory cells capable of being electrically overwritten within the non-volatile memory cell array, and an erase marker corresponding to the data unit and indicating whether the data unit is in an erased state or a not-erased state.

摘要翻译： 公开了一种非易失性存储器件，非易失性存储单元阵列和相关的操作方法。 非易失性存储单元阵列包括存储在能够在非易失性存储单元阵列内被电覆盖的多个非易失性存储单元中的定义数据单元，以及与数据单元对应的擦除标记，并指示数据 单元处于擦除状态或未擦除状态。

公开(公告)号：US08045387B2

公开(公告)日：2011-10-25

申请号：US12509612

申请日：2009-07-27

申请人： Ki-Tae Park ,  Yeong-Taek Lee ,  Soon-Wook Hwang ,  Young-Wook Jeong

发明人： Ki-Tae Park ,  Yeong-Taek Lee ,  Soon-Wook Hwang ,  Young-Wook Jeong

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/12 ,  G11C16/0483

摘要： A flash memory and programming method are disclosed. The flash memory includes a memory cell array having memory cells arranged in a plurality of word lines including a selected word line and a plurality of non-selected word lines and a plurality of bit lines, a high voltage generator generating a program voltage applied to the selected word line, and a pass voltage applied to at least one of the non-selected word lines adjacent to the selected word line, and control logic controlling the generation of the program voltage, such that the program voltage is incrementally increased during a program operation, and generation of the pass voltage, such that the program voltage is incrementally increased.

摘要翻译： 公开了闪存和编程方法。 闪速存储器包括存储单元阵列，该存储单元阵列具有布置在包括所选择的字线和多个未选择的字线和多个位线的多个字线中的存储器单元，高电压发生器产生施加到该字线的编程电压 所选择的字线和施加到与所选字线相邻的未选择的字线中的至少一个的通过电压，以及控制逻辑，以控制编程电压的产生，使得编程电压在编程操作期间递增地增加 ，并产生通过电压，使得编程电压递增地增加。

公开(公告)号：US20110235432A1

公开(公告)日：2011-09-29

申请号：US13153285

申请日：2011-06-03

申请人： Doo-Gon Kim ,  Ki-Tae Park ,  Yeong-Taek Lee

发明人： Doo-Gon Kim ,  Ki-Tae Park ,  Yeong-Taek Lee

IPC分类号： G11C16/28

CPC分类号： G11C16/14

摘要： An erasing method of post-programming in a nonvolatile memory device. The method includes post-programming dummy memory cells; verifying whether threshold voltages of the dummy memory cells are greater than or equal to a first voltage; post-programming normal memory cells; and verifying whether threshold voltages of the normal memory cells are greater than or equal to a second voltage. The first voltage is different from the second voltage.

摘要翻译： 一种在非易失性存储器件中进行后编程的擦除方法。 该方法包括后编程虚拟存储器单元; 验证所述伪存储单元的阈值电压是否大于或等于第一电压; 后编程正常记忆单元; 以及验证所述正常存储单元的阈值电压是否大于或等于第二电压。 第一电压与第二电压不同。

公开(公告)号：US07986560B2

公开(公告)日：2011-07-26

申请号：US12558717

申请日：2009-09-14

申请人： Ki-Tae Park ,  Yong-Seok Kim ,  Ki-Nam Kim ,  Yeong-Taek Lee

发明人： Ki-Tae Park ,  Yong-Seok Kim ,  Ki-Nam Kim ,  Yeong-Taek Lee

IPC分类号： G11C11/34

CPC分类号： G11C16/344 ,  G11C16/3454

摘要： Disclosed is a method of verifying a programmed condition of a flash memory device, being comprised of: determining a level of an additional verifying voltage in response to the number of programming/erasing cycles of memory cells; conducting a verifying operation to programmed memory cells with an initial verifying voltage lower than the additional verifying voltage; and selectively conducting an additional verifying operation with the additional verifying voltage to the program-verified memory cells in response to the number of programming/erasing cycles.

摘要翻译： 公开了一种验证闪速存储器件的编程状态的方法，其包括：响应于存储器单元的编程/擦除循环的数量确定额外的验证电压的电平; 对初始验证电压低于附加验证电压的程序存储单元执行验证操作; 以及响应于所述编程/擦除周期的数量，选择性地对所述经过程序验证的存储器单元执行附加验证电压的附加验证操作。

公开(公告)号：US07957199B2

公开(公告)日：2011-06-07

申请号：US12833098

申请日：2010-07-09

申请人： Doo-Gon Kim ,  Ki-Tae Park ,  Yeong-Taek Lee

发明人： Doo-Gon Kim ,  Ki-Tae Park ,  Yeong-Taek Lee

IPC分类号： G11C16/06

CPC分类号： G11C16/14

摘要： An erasing method in a nonvolatile memory device is disclosed. The method includes post-programming dummy memory cells; verifying whether threshold voltages of the dummy memory cells are greater than or equal to a first voltage; post-programming normal memory cells; and verifying whether threshold voltages of the normal memory cells are greater than or equal to a second voltage. The first voltage is different from the second voltage, and the post-programming of the dummy memory cells comprises: applying a program voltage to a plurality of dummy word lines coupled to the dummy memory cells to post-program the dummy memory cells; and applying a pass voltage to a plurality of normal word lines coupled to the normal memory cells so that the normal memory cells are not post-programmed.

摘要翻译： 公开了一种非易失性存储器件中的擦除方法。 该方法包括后编程虚拟存储器单元; 验证所述伪存储单元的阈值电压是否大于或等于第一电压; 后编程正常记忆单元; 以及验证所述正常存储单元的阈值电压是否大于或等于第二电压。 第一电压与第二电压不同，并且虚拟存储单元的后编程包括：将程序电压施加到耦合到虚拟存储器单元的多个虚拟字线，以对虚拟存储器单元进行后编程; 以及对耦合到所述正常存储器单元的多个正常字线施加通过电压，使得所述正常存储器单元未被编程。