公开(公告)号：US20110169173A1

公开(公告)日：2011-07-14

申请号：US13005051

申请日：2011-01-12

申请人： Sung-Ho MUN ,  Sun-Won Kang

发明人： Sung-Ho MUN ,  Sun-Won Kang

IPC分类号： H01L23/48

CPC分类号： H01L24/48 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/48471 ,  H01L2224/49112 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/85196 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A wiring substrate for a semiconductor chip includes a substrate having a first surface and a second surface opposite to the first surface. The substrate has at least one slot from the first surface to the second surface that exposes chip pads of a semiconductor chip mounted to the first surface. The substrate has first and second regions divided by the slot. A plurality of bonding pads is arranged along both side portions of the slot and the bonding pads are connected to bonding wires that are drawn from the chip pads through the slot. First and second conductive patterns are respectively formed in the first and second regions and respectively connected to the at least one bonding pad. A merging pattern extends from the first region to the second region to electrically connect the first conductive pattern and the second conductive pattern. A merging wire electrically connects the merging pattern and the at least one chip pad.

摘要翻译： 用于半导体芯片的布线基板包括具有与第一表面相对的第一表面和第二表面的基板。 衬底具有从第一表面到第二表面的至少一个槽，其暴露安装到第一表面的半导体芯片的芯片焊盘。 衬底具有由槽划分的第一和第二区域。 多个接合焊盘沿着槽的两侧布置，并且焊盘与从芯片焊盘通过槽拉出的接合线连接。 第一和第二导电图案分别形成在第一和第二区域中，并且分别连接到至少一个接合焊盘。 合并图案从第一区域延伸到第二区域以电连接第一导电图案和第二导电图案。 合并线将合并图案与至少一个芯片垫电连接。