公开(公告)号：US20170179065A1

公开(公告)日：2017-06-22

申请号：US15378029

申请日：2016-12-13

申请人： Samsung Electronics Co., Ltd.

发明人： Hyosung KOO

IPC分类号： H01L23/00

CPC分类号： H01L24/48 ,  H01L24/45 ,  H01L24/78 ,  H01L24/85 ,  H01L2224/05599 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48458 ,  H01L2224/48465 ,  H01L2224/78301 ,  H01L2224/85045 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2224/85196 ,  H01L2224/85345 ,  H01L2924/00014 ,  H01L2224/85399

摘要： An electrical interconnection includes a wire loop having a first end bonded to a first bonding site using a first bonding portion, and a second end bonded to a second bonding site using a second bonding portion. The second bonding portion includes a folded portion having a wire that extends from the second end of the wire loop and is folded on the second bonding site. The folded portion includes a first folded portion connected to the second end of the wire loop and extending toward the first bonding site, a second folded portion provided on the first folded portion, and a tail protruding from a portion of the second folded portion. An interface is formed between the first and second folded portions. A top surface of the second folded portion includes an inclined surface recessed toward the first folded portion.

公开(公告)号：US20180331064A1

公开(公告)日：2018-11-15

申请号：US16040507

申请日：2018-07-19

申请人： Samsung Electronics Co., Ltd.

发明人： Hyosung KOO

IPC分类号： H01L23/00

CPC分类号： H01L24/48 ,  H01L24/45 ,  H01L24/78 ,  H01L24/85 ,  H01L2224/05599 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48458 ,  H01L2224/48465 ,  H01L2224/78301 ,  H01L2224/85045 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2224/85196 ,  H01L2224/85345 ,  H01L2924/00014 ,  H01L2224/85399

摘要： An electrical interconnection includes a wire loop having a first end bonded to a first bonding site using a first bonding portion, and a second end bonded to a second bonding site using a second bonding portion. The second bonding portion includes a folded portion having a wire that extends from the second end of the wire loop and is folded on the second bonding site. The folded portion includes a first folded portion connected to the second end of the wire loop and extending toward the first bonding site, a second folded portion provided on the first folded portion, and a tail protruding from a portion of the second folded portion. An interface is formed between the first and second folded portions. A top surface of the second folded portion includes an inclined surface recessed toward the first folded portion.

公开(公告)号：US20110169173A1

公开(公告)日：2011-07-14

申请号：US13005051

申请日：2011-01-12

申请人： Sung-Ho MUN ,  Sun-Won Kang

发明人： Sung-Ho MUN ,  Sun-Won Kang

IPC分类号： H01L23/48

CPC分类号： H01L24/48 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/48471 ,  H01L2224/49112 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/85196 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A wiring substrate for a semiconductor chip includes a substrate having a first surface and a second surface opposite to the first surface. The substrate has at least one slot from the first surface to the second surface that exposes chip pads of a semiconductor chip mounted to the first surface. The substrate has first and second regions divided by the slot. A plurality of bonding pads is arranged along both side portions of the slot and the bonding pads are connected to bonding wires that are drawn from the chip pads through the slot. First and second conductive patterns are respectively formed in the first and second regions and respectively connected to the at least one bonding pad. A merging pattern extends from the first region to the second region to electrically connect the first conductive pattern and the second conductive pattern. A merging wire electrically connects the merging pattern and the at least one chip pad.

摘要翻译： 用于半导体芯片的布线基板包括具有与第一表面相对的第一表面和第二表面的基板。 衬底具有从第一表面到第二表面的至少一个槽，其暴露安装到第一表面的半导体芯片的芯片焊盘。 衬底具有由槽划分的第一和第二区域。 多个接合焊盘沿着槽的两侧布置，并且焊盘与从芯片焊盘通过槽拉出的接合线连接。 第一和第二导电图案分别形成在第一和第二区域中，并且分别连接到至少一个接合焊盘。 合并图案从第一区域延伸到第二区域以电连接第一导电图案和第二导电图案。 合并线将合并图案与至少一个芯片垫电连接。

公开(公告)号：US20100311234A1

公开(公告)日：2010-12-09

申请号：US12789957

申请日：2010-05-28

申请人： Yukinori Tabira

发明人： Yukinori Tabira

IPC分类号： H01L21/44 ,  B23K31/02 ,  B23K37/04 ,  B23K37/00

CPC分类号： H01L24/48 ,  B23K20/007 ,  H01L24/49 ,  H01L24/78 ,  H01L24/85 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/4945 ,  H01L2224/78301 ,  H01L2224/85045 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2224/85191 ,  H01L2224/85196 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A method of manufacturing a semiconductor device is provided. A first bond of a first wire loop is formed. A wire is bonded through a ball to a lead or a chip electrode of a semiconductor chip to form a second bond of the first wire loop and a first bond of a second wire loop. A second bond of the second wire loop is formed. The ball provides a large bonding area, and thus, provides a strong bonding strength.

摘要翻译： 提供一种制造半导体器件的方法。 形成第一线环的第一键。 线通过球接合到半导体芯片的引线或芯片电极，以形成第一线圈的第二接合和第二线圈的第一接合。 形成第二线圈的第二接合。 球提供了大的粘接面积，因此提供了很强的粘合强度。