公开(公告)号：US08619452B2

公开(公告)日：2013-12-31

申请号：US11515223

申请日：2006-09-01

申请人： Suresh N. Rajan ,  Michael J. S. Smith ,  David T Wang

发明人： Suresh N. Rajan ,  Michael J. S. Smith ,  David T Wang

IPC分类号： G11C5/02

CPC分类号： G11C7/00 ,  G11C5/02 ,  G11C7/10 ,  G11C11/4093 ,  G11C29/812

摘要： Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.

公开(公告)号：US08089795B2

公开(公告)日：2012-01-03

申请号：US11702981

申请日：2007-02-05

申请人： Suresh N. Rajan ,  Keith R Schakel ,  Michael J. S. Smith ,  David T Wang ,  Frederick Daniel Weber

发明人： Suresh N. Rajan ,  Keith R Schakel ,  Michael J. S. Smith ,  David T Wang ,  Frederick Daniel Weber

IPC分类号： G11C5/06

CPC分类号： G11C11/4093 ,  G06F12/00 ,  G11C5/00 ,  G11C7/10 ,  G11C7/1045 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/15311

摘要： A memory module, which includes at least one memory stack, comprises a plurality of DRAM integrated circuits and an interface circuit. The interface circuit interfaces the memory stack to a host system so as to operate the memory stack as a single DRAM integrated circuit. In other embodiments, a memory module includes at least one memory stack and a buffer integrated circuit. The buffer integrated circuit, coupled to a host system, interfaces the memory stack to the host system so to operate the memory stack as at least two DRAM integrated circuits. In yet other embodiments, an interface circuit maps virtual addresses from the host system to physical addresses of the DRAM integrated circuits in a linear manner. In a further embodiment, the interface circuit maps one or more banks of virtual addresses from the host system to a single one of the DRAM integrated circuits. In yet other embodiments, the buffer circuit interfaces the memory stack to the host system for transforming one or more physical parameters between the DRAM integrated circuits and the host system. In still other embodiments, the buffer circuit interfaces the memory stack to the host system for configuring one or more of the DRAM integrated circuits in the memory stack. Neither the patentee nor the USPTO intends for details set forth in the abstract to constitute limitations to claims not explicitly reciting those details.

摘要翻译： 包括至少一个存储器堆栈的存储器模块包括多个DRAM集成电路和接口电路。 接口电路将存储器堆栈连接到主机系统，以便将存储器堆栈操作为单个DRAM集成电路。 在其他实施例中，存储器模块包括至少一个存储器堆栈和缓冲器集成电路。 耦合到主机系统的缓冲器集成电路将存储器堆栈连接到主机系统，以便将存储器堆栈操作为至少两个DRAM集成电路。 在其他实施例中，接口电路以虚线方式将虚拟地址从主机系统映射到DRAM集成电路的物理地址。 在另一个实施例中，接口电路将来自主机系统的一个或多个虚拟地址组映射到DRAM集成电路的单个地址。 在其他实施例中，缓冲电路将存储器堆栈接口到主机系统，用于在DRAM集成电路和主机系统之间转换一个或多个物理参数。 在其他实施例中，缓冲电路将存储器堆栈接口到主机系统，用于配置存储器堆叠中的一个或多个DRAM集成电路。 专利权人和美国专利商标局均不打算在摘要中规定的细节构成对明确陈述这些细节的权利要求的限制。

公开(公告)号：US20130100746A1

公开(公告)日：2013-04-25

申请号：US13620565

申请日：2012-09-14

申请人： Suresh N. Rajan ,  Michael J. S. Smith ,  David T. Wang

发明人： Suresh N. Rajan ,  Michael J. S. Smith ,  David T. Wang

IPC分类号： G11C7/00

CPC分类号： G11C7/00 ,  G11C5/02 ,  G11C7/10 ,  G11C11/4093 ,  G11C29/812

摘要： Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.

摘要翻译： 使用堆叠式存储器集成电路或芯片构建大容量存储器系统。 堆叠的存储器芯片被构造成在满足当前和将来的存储器标准的同时消除诸如信号完整性的问题。

公开(公告)号：US08566556B2

公开(公告)日：2013-10-22

申请号：US13341844

申请日：2011-12-30

申请人： Suresh Natarajan Rajan ,  Keith R. Schakel ,  Michael J. S. Smith ,  David T. Wang ,  Frederick Daniel Weber

发明人： Suresh Natarajan Rajan ,  Keith R. Schakel ,  Michael J. S. Smith ,  David T. Wang ,  Frederick Daniel Weber

IPC分类号： G06F12/02

CPC分类号： G11C11/4093 ,  G06F12/00 ,  G11C5/00 ,  G11C7/10 ,  G11C7/1045 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/15311

摘要： A memory module, which includes at least one memory stack, comprises a plurality of DRAM integrated circuits and an interface circuit. The interface circuit interfaces the memory stack to a host system so as to operate the memory stack as a single DRAM integrated circuit. In other embodiments, a memory module includes at least one memory stack and a buffer integrated circuit. The buffer integrated circuit, coupled to a host system, interfaces the memory stack to the host system so to operate the memory stack as at least two DRAM integrated circuits. In yet other embodiments, the buffer circuit interfaces the memory stack to the host system for transforming one or more physical parameters between the DRAM integrated circuits and the host system.

摘要翻译： 包括至少一个存储器堆栈的存储器模块包括多个DRAM集成电路和接口电路。 接口电路将存储器堆栈连接到主机系统，以便将存储器堆栈操作为单个DRAM集成电路。 在其他实施例中，存储器模块包括至少一个存储器堆栈和缓冲器集成电路。 耦合到主机系统的缓冲器集成电路将存储器堆栈连接到主机系统，以便将存储器堆栈操作为至少两个DRAM集成电路。 在其他实施例中，缓冲电路将存储器堆栈接口到主机系统，用于在DRAM集成电路和主机系统之间转换一个或多个物理参数。

公开(公告)号：US08438328B2

公开(公告)日：2013-05-07

申请号：US12378328

申请日：2009-02-14

申请人： Michael J. S. Smith ,  Suresh Natarajan Rajan ,  David T. Wang

发明人： Michael J. S. Smith ,  Suresh Natarajan Rajan ,  David T. Wang

IPC分类号： G06F12/00

CPC分类号： G06F13/4239 ,  Y02D10/14 ,  Y02D10/151

摘要： One embodiment of the present invention sets forth an abstracted memory subsystem comprising abstracted memories, which each may be configured to present memory-related characteristics onto a memory system interface. The characteristics can be presented on the memory system interface via logic signals or protocol exchanges, and the characteristics may include any one or more of, an address space, a protocol, a memory type, a power management rule, a number of pipeline stages, a number of banks, a mapping to physical banks, a number of ranks, a timing characteristic, an address decoding option, a bus turnaround time parameter, an additional signal assertion, a sub-rank, a number of planes, or other memory-related characteristics. Some embodiments include an intelligent register device and/or, an intelligent buffer device. One advantage of the disclosed subsystem is that memory performance may be optimized regardless of the specific protocols used by the underlying memory hardware devices.

公开(公告)号：US08797779B2

公开(公告)日：2014-08-05

申请号：US13620425

申请日：2012-09-14

申请人： Suresh Natarajan Rajan ,  Keith R. Schakel ,  Michael J. S. Smith ,  David T. Wang ,  Frederick Daniel Weber

发明人： Suresh Natarajan Rajan ,  Keith R. Schakel ,  Michael J. S. Smith ,  David T. Wang ,  Frederick Daniel Weber

IPC分类号： G11C5/06 ,  G11C11/4093

CPC分类号： G11C11/4093 ,  G06F12/00 ,  G11C5/00 ,  G11C7/10 ,  G11C7/1045 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/15311

摘要： A memory module, which includes at least one memory stack, comprises a plurality of DRAM integrated circuits and an interface circuit. The interface circuit interfaces the memory stack to a host system so as to operate the memory stack as a single DRAM integrated circuit. In other embodiments, a memory module includes at least one memory stack and a buffer integrated circuit. The buffer integrated circuit, coupled to a host system, interfaces the memory stack to the host system so to operate the memory stack as at least two DRAM integrated circuits. In yet other embodiments, the buffer circuit interfaces the memory stack to the host system for transforming one or more physical parameters between the DRAM integrated circuits and the host system.

摘要翻译： 包括至少一个存储器堆栈的存储器模块包括多个DRAM集成电路和接口电路。 接口电路将存储器堆栈连接到主机系统，以便将存储器堆栈操作为单个DRAM集成电路。 在其他实施例中，存储器模块包括至少一个存储器堆栈和缓冲器集成电路。 耦合到主机系统的缓冲器集成电路将存储器堆栈连接到主机系统，以便将存储器堆栈操作为至少两个DRAM集成电路。 在其他实施例中，缓冲电路将存储器堆栈接口到主机系统，用于在DRAM集成电路和主机系统之间转换一个或多个物理参数。

公开(公告)号：US20120233395A1

公开(公告)日：2012-09-13

申请号：US13473827

申请日：2012-05-17

申请人： Michael J. S. Smith ,  Suresh Natarajan Rajan ,  David T. Wang

发明人： Michael J. S. Smith ,  Suresh Natarajan Rajan ,  David T. Wang

IPC分类号： G06F12/00

CPC分类号： G06F13/4239 ,  Y02D10/14 ,  Y02D10/151

摘要： One embodiment of the present invention sets forth an abstracted memory subsystem comprising abstracted memories, which each may be configured to present memory related characteristics onto a memory system interface. The characteristics can be presented on the memory system interface via logic signals or protocol exchanges, and the characteristics may include any one or more of, an address space, a protocol, a memory type, a power management rule, a number of pipeline stages, a number of banks, a mapping to physical banks, a number of ranks, a timing characteristic, an address decoding option, a bus turnaround time parameter, an additional signal assertion, a sub-rank, a number of planes, or other memory-related characteristics. Some embodiments include an intelligent register device and/or, an intelligent buffer device. One advantage of the disclosed subsystem is that memory performance may be optimized regardless of the specific protocols used by the underlying memory hardware devices.

摘要翻译： 本发明的一个实施例提出了一种抽象存储器子系统，其包括抽象存储器，每个存储器子系统可被配置为将存储器相关特性呈现到存储器系统接口上。 该特性可以通过逻辑信号或协议交换在存储器系统接口上呈现，并且特征可以包括地址空间，协议，存储器类型，功率管理规则，多个流水线级中的任何一个或多个， 多个银行，映射到物理银行，多个等级，定时特征，地址解码选项，总线周转时间参数，附加信号断言，子秩，多个平面或其他存储器 - 相关特征 一些实施例包括智能寄存器装置和/或智能缓冲器装置。 所公开的子系统的一个优点是可以优化存储器性能，而不管底层存储器硬件设备使用的特定协议。

公开(公告)号：US08751732B2

公开(公告)日：2014-06-10

申请号：US13620424

申请日：2012-09-14

申请人： Radoslav Danilak ,  Michael J. S. Smith ,  Suresh Rajan

发明人： Radoslav Danilak ,  Michael J. S. Smith ,  Suresh Rajan

IPC分类号： G06F12/00 ,  G06F12/02

CPC分类号： G06F12/0246 ,  G06F3/0679 ,  G06F13/385

摘要： In one embodiment, an interface circuit is configured to couple to one or more flash memory devices and is further configured to couple to a host system. The interface circuit is configured to present at least one virtual flash memory device to the host system, wherein the interface circuit is configured to implement the virtual flash memory device using the one or more flash memory devices to which the interface circuit is coupled.

摘要翻译： 在一个实施例中，接口电路被配置为耦合到一个或多个闪存设备，并且还被配置为耦合到主机系统。 接口电路被配置为向主机系统呈现至少一个虚拟闪存设备，其中接口电路被配置为使用接口电路耦合到的一个或多个闪存设备来实现虚拟闪存设备。

公开(公告)号：US08386833B2

公开(公告)日：2013-02-26

申请号：US13280251

申请日：2011-10-24

申请人： Michael J. S. Smith ,  Suresh Natarajan Rajan

发明人： Michael J. S. Smith ,  Suresh Natarajan Rajan

IPC分类号： G06F11/00

CPC分类号： G06F12/00 ,  G01K13/00 ,  G06F11/1076 ,  G06F11/26 ,  G06F13/1668 ,  G06F15/7821 ,  G06F17/00 ,  G11C7/10 ,  G11C7/1012 ,  G11C7/1045 ,  G11C8/12 ,  G11C11/401 ,  G11C11/4076 ,  G11C11/4093 ,  G11C29/02 ,  G11C29/022 ,  G11C29/028 ,  G11C29/24 ,  G11C29/50 ,  G11C29/50012 ,  G11C2207/2254 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/15311

摘要： One embodiment of the present invention sets forth a memory module that includes at least one memory chip, and an intelligent chip coupled to the at least one memory chip and a memory controller, where the intelligent chip is configured to implement at least a part of a RAS feature. The disclosed architecture allows one or more RAS features to be implemented locally to the memory module using one or more intelligent register chips, one or more intelligent buffer chips, or some combination thereof. Such an approach not only increases the effectiveness of certain RAS features that were available in prior art systems, but also enables the implementation of certain RAS features that were not available in prior art systems.

摘要翻译： 本发明的一个实施例提出了一种存储器模块，其包括至少一个存储器芯片和耦合到所述至少一个存储器芯片和存储器控制器的智能芯片，其中智能芯片被配置为实现至少一部分 RAS功能。 所公开的架构允许使用一个或多个智能寄存器芯片，一个或多个智能缓冲器芯片或其某些组合在本地对存储器模块实现一个或多个RAS特征。 这种方法不仅增加了现有技术系统中可用的某些RAS特征的有效性，而且还使得能够实现在现有技术系统中不可用的某些RAS特征。

公开(公告)号：US06326806B1

公开(公告)日：2001-12-04

申请号：US09539163

申请日：2000-03-29

申请人： Hamish T. Fallside ,  Michael J. S. Smith

发明人： Hamish T. Fallside ,  Michael J. S. Smith

IPC分类号： G06F738

CPC分类号： G06F17/5054 ,  G06F15/7867

摘要： An FPGA-based communications access point and system for reconfiguration of the FPGA via a communications channel are described in various embodiments. One embodiment includes a physical interface circuit, a storage element (e.g., a RAM), an FPGA, and a configuration control circuit. The physical interface circuit is arranged for connection to a communications channel and is coupled to the FPGA. The configuration control circuit includes a controlling circuit (e.g., a PLD) and a memory circuit (e.g., a PROM). The PROM is configured with an initial configuration bitstream for the FPGA. The initial configuration bitstream implements both a communications protocol and a control function that writes configuration bits received by the FPGA via the communications channel to the RAM. The control function also generates a reconfiguration signal responsive to a first predetermined condition. The PLD is configured to load the initial configuration bitstream from the PROM into the FPGA, and, responsive to the reconfiguration signal from the FPGA, to load a second configuration bitstream from the RAM into the FPGA. The control function may be configured to interact with standard network programs such as FTP (file transfer protocol) or custom programs.

摘要翻译： 在各种实施例中描述了用于通过通信信道重新配置FPGA的基于FPGA的通信接入点和系统。 一个实施例包括物理接口电路，存储元件（例如RAM），FPGA和配置控制电路。 物理接口电路被布置为连接到通信信道并且耦合到FPGA。 配置控制电路包括控制电路（例如PLD）和存储电路（例如，PROM）。 PROM配置有FPGA的初始配置位流。 初始配置比特流实现通信协议和控制功能，该功能将通过通信通道将FPGA接收的配置位写入RAM。 控制功能还响应于第一预定条件产生重新配置信号。 PLD被配置为将来自PROM的初始配置比特流加载到FPGA中，并且响应于来自FPGA的重新配置信号，将第二配置比特流从RAM加载到FPGA中。 控制功能可以配置为与诸如FTP（文件传输协议）或定制程序的标准网络程序交互。