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    Emulation of abstracted DIMMs using abstracted DRAMs
    1.
    发明授权
    Emulation of abstracted DIMMs using abstracted DRAMs 有权

    公开(公告)号：US08438328B2

    公开(公告)日：2013-05-07

    申请号：US12378328

    申请日：2009-02-14

    申请人： Michael J. S. Smith ,  Suresh Natarajan Rajan ,  David T. Wang

    发明人： Michael J. S. Smith ,  Suresh Natarajan Rajan ,  David T. Wang

    IPC分类号： G06F12/00

    CPC分类号： G06F13/4239 ,  Y02D10/14 ,  Y02D10/151

    摘要： One embodiment of the present invention sets forth an abstracted memory subsystem comprising abstracted memories, which each may be configured to present memory-related characteristics onto a memory system interface. The characteristics can be presented on the memory system interface via logic signals or protocol exchanges, and the characteristics may include any one or more of, an address space, a protocol, a memory type, a power management rule, a number of pipeline stages, a number of banks, a mapping to physical banks, a number of ranks, a timing characteristic, an address decoding option, a bus turnaround time parameter, an additional signal assertion, a sub-rank, a number of planes, or other memory-related characteristics. Some embodiments include an intelligent register device and/or, an intelligent buffer device. One advantage of the disclosed subsystem is that memory performance may be optimized regardless of the specific protocols used by the underlying memory hardware devices.

    Memory module with memory stack and interface with enhanced capabilities
    2.
    发明授权
    Memory module with memory stack and interface with enhanced capabilities 有权
    内存模块，具有内存堆栈和具有增强功能的接口

    公开(公告)号：US08566556B2

    公开(公告)日：2013-10-22

    申请号：US13341844

    申请日：2011-12-30

    申请人： Suresh Natarajan Rajan ,  Keith R. Schakel ,  Michael J. S. Smith ,  David T. Wang ,  Frederick Daniel Weber

    发明人： Suresh Natarajan Rajan ,  Keith R. Schakel ,  Michael J. S. Smith ,  David T. Wang ,  Frederick Daniel Weber

    IPC分类号： G06F12/02

    CPC分类号： G11C11/4093 ,  G06F12/00 ,  G11C5/00 ,  G11C7/10 ,  G11C7/1045 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/15311

    摘要： A memory module, which includes at least one memory stack, comprises a plurality of DRAM integrated circuits and an interface circuit. The interface circuit interfaces the memory stack to a host system so as to operate the memory stack as a single DRAM integrated circuit. In other embodiments, a memory module includes at least one memory stack and a buffer integrated circuit. The buffer integrated circuit, coupled to a host system, interfaces the memory stack to the host system so to operate the memory stack as at least two DRAM integrated circuits. In yet other embodiments, the buffer circuit interfaces the memory stack to the host system for transforming one or more physical parameters between the DRAM integrated circuits and the host system.

    摘要翻译： 包括至少一个存储器堆栈的存储器模块包括多个DRAM集成电路和接口电路。 接口电路将存储器堆栈连接到主机系统，以便将存储器堆栈操作为单个DRAM集成电路。 在其他实施例中，存储器模块包括至少一个存储器堆栈和缓冲器集成电路。 耦合到主机系统的缓冲器集成电路将存储器堆栈连接到主机系统，以便将存储器堆栈操作为至少两个DRAM集成电路。 在其他实施例中，缓冲电路将存储器堆栈接口到主机系统，用于在DRAM集成电路和主机系统之间转换一个或多个物理参数。

    Memory module with memory stack and interface with enhanced capabilites
    3.
    发明授权
    Memory module with memory stack and interface with enhanced capabilites 有权
    具有内存堆栈的内存模块和具有增强功能的界面

    公开(公告)号：US08797779B2

    公开(公告)日：2014-08-05

    申请号：US13620425

    申请日：2012-09-14

    申请人： Suresh Natarajan Rajan ,  Keith R. Schakel ,  Michael J. S. Smith ,  David T. Wang ,  Frederick Daniel Weber

    发明人： Suresh Natarajan Rajan ,  Keith R. Schakel ,  Michael J. S. Smith ,  David T. Wang ,  Frederick Daniel Weber

    IPC分类号： G11C5/06 ,  G11C11/4093

    CPC分类号： G11C11/4093 ,  G06F12/00 ,  G11C5/00 ,  G11C7/10 ,  G11C7/1045 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/15311

    摘要： A memory module, which includes at least one memory stack, comprises a plurality of DRAM integrated circuits and an interface circuit. The interface circuit interfaces the memory stack to a host system so as to operate the memory stack as a single DRAM integrated circuit. In other embodiments, a memory module includes at least one memory stack and a buffer integrated circuit. The buffer integrated circuit, coupled to a host system, interfaces the memory stack to the host system so to operate the memory stack as at least two DRAM integrated circuits. In yet other embodiments, the buffer circuit interfaces the memory stack to the host system for transforming one or more physical parameters between the DRAM integrated circuits and the host system.

    摘要翻译： 包括至少一个存储器堆栈的存储器模块包括多个DRAM集成电路和接口电路。 接口电路将存储器堆栈连接到主机系统，以便将存储器堆栈操作为单个DRAM集成电路。 在其他实施例中，存储器模块包括至少一个存储器堆栈和缓冲器集成电路。 耦合到主机系统的缓冲器集成电路将存储器堆栈连接到主机系统，以便将存储器堆栈操作为至少两个DRAM集成电路。 在其他实施例中，缓冲电路将存储器堆栈接口到主机系统，用于在DRAM集成电路和主机系统之间转换一个或多个物理参数。

    EMULATION OF ABSTRACTED DIMMS USING ABSTRACTED DRAMS
    4.
    发明申请
    EMULATION OF ABSTRACTED DIMMS USING ABSTRACTED DRAMS 有权
    使用ABSTRACED DRAMS模拟抽象尺寸

    公开(公告)号：US20120233395A1

    公开(公告)日：2012-09-13

    申请号：US13473827

    申请日：2012-05-17

    申请人： Michael J. S. Smith ,  Suresh Natarajan Rajan ,  David T. Wang

    发明人： Michael J. S. Smith ,  Suresh Natarajan Rajan ,  David T. Wang

    IPC分类号： G06F12/00

    CPC分类号： G06F13/4239 ,  Y02D10/14 ,  Y02D10/151

    摘要： One embodiment of the present invention sets forth an abstracted memory subsystem comprising abstracted memories, which each may be configured to present memory related characteristics onto a memory system interface. The characteristics can be presented on the memory system interface via logic signals or protocol exchanges, and the characteristics may include any one or more of, an address space, a protocol, a memory type, a power management rule, a number of pipeline stages, a number of banks, a mapping to physical banks, a number of ranks, a timing characteristic, an address decoding option, a bus turnaround time parameter, an additional signal assertion, a sub-rank, a number of planes, or other memory-related characteristics. Some embodiments include an intelligent register device and/or, an intelligent buffer device. One advantage of the disclosed subsystem is that memory performance may be optimized regardless of the specific protocols used by the underlying memory hardware devices.

    摘要翻译： 本发明的一个实施例提出了一种抽象存储器子系统，其包括抽象存储器，每个存储器子系统可被配置为将存储器相关特性呈现到存储器系统接口上。 该特性可以通过逻辑信号或协议交换在存储器系统接口上呈现，并且特征可以包括地址空间，协议，存储器类型，功率管理规则，多个流水线级中的任何一个或多个， 多个银行，映射到物理银行，多个等级，定时特征，地址解码选项，总线周转时间参数，附加信号断言，子秩，多个平面或其他存储器 - 相关特征 一些实施例包括智能寄存器装置和/或智能缓冲器装置。 所公开的子系统的一个优点是可以优化存储器性能，而不管底层存储器硬件设备使用的特定协议。

    Memory apparatus operable to perform a power-saving operation
    9.
    发明授权
    Memory apparatus operable to perform a power-saving operation 有权
    可操作以执行省电操作的存储装置

    公开(公告)号：US08595419B2

    公开(公告)日：2013-11-26

    申请号：US13182234

    申请日：2011-07-13

    申请人： Suresh Natarajan Rajan ,  Keith R. Schakel ,  Michael John Sebastian Smith ,  David T. Wang ,  Frederick Daniel Weber

    发明人： Suresh Natarajan Rajan ,  Keith R. Schakel ,  Michael John Sebastian Smith ,  David T. Wang ,  Frederick Daniel Weber

    IPC分类号： G06F12/00

    CPC分类号： G11C7/1072 ,  G06F13/4243 ,  G11C7/10 ,  G11C11/406 ,  G11C11/40618 ,  Y02D10/14 ,  Y02D10/151

    摘要： A memory apparatus includes multiple memory circuits and an interface circuit to present to a host system emulated memory circuits. The interface circuit includes a first component of a first type and a second component of a second type, the first component and the second component being operable to present a host-system interface to the host system and to present a memory-circuit interface to the plurality of memory circuits, in which there is a difference in at least one aspect between the host-system interface and the memory circuit interface. At least one of the first and second components is operable to identify one or more memory circuits that is not being accessed and to perform a power-saving operation on the one or more memory circuits identified as not being accessed, where the power-saving operation includes placing the memory circuits identified as not being accessed in a precharge power down mode.

    摘要翻译： 存储装置包括多个存储器电路和用于向主机系统呈现仿真存储器电路的接口电路。 接口电路包括第一类型的第一组件和第二类型的第二组件，第一组件和第二组件可操作以向主机系统呈现主机系统接口并向存储器电路接口呈现存储器电路接口 多个存储器电路，其中在主机系统接口和存储器电路接口之间的至少一个方面存在差异。 第一和第二组件中的至少一个可操作以识别未被访问的一个或多个存储器电路，并且对被识别为未访问的一个或多个存储器电路进行功率保存操作，其中省电操作 包括将识别为未被访问的存储器电路放置在预充电掉电模式中。