公开(公告)号：US12302642B2

公开(公告)日：2025-05-13

申请号：US18760500

申请日：2024-07-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Kuang-Ching Chang ,  Jung-Chan Yang ,  Hui-Zhong Zhuang ,  Chih-Liang Chen ,  Kuo-Nan Yang

IPC: G06F1/3287 ,  H10D89/10

Abstract: An integrated circuit includes a first power rail on a back-side of a wafer and being configured to supply a first voltage, a header circuit coupled to the first power rail and being configured to supply the first voltage to the first power rail, a second and third power rail on the back-side of the wafer, a fourth power rail on a front-side of the wafer, and a fifth power rail on the back-side of the wafer. The second and third power rail being configured to supply a second voltage. The fourth power rail includes a first set of conductors configured to supply a third voltage to the header circuit. The fifth power rail is configured to supply the third voltage and is separated from the first power rail in a first and second direction, and is separated from the second and third power rail in the first direction.

公开(公告)号：US12299373B2

公开(公告)日：2025-05-13

申请号：US18447187

申请日：2023-08-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chi-Yu Lu ,  Hui-Zhong Zhuang ,  Pin-Dai Sue ,  Yi-Hsin Ko ,  Li-Chun Tien

IPC: G06F30/392 ,  G06F30/398

Abstract: A method of designing a semiconductor device including the operations of analyzing a vertical abutment between a first standard cell block and a second cell block and, if a mismatch is identified between the first standard cell block and the second cell block initiating the selection of a first modified cell block that reduces the mismatch and a spacing between the first modified cell block and the second cell block, the first modified cell block comprising a first abutment region having a continuous active region arranged along a first axis parallel to an edge of the vertical abutment, and replacing the first standard cell block with the first modified cell block to obtain a first modified layout design and devices manufactured according to the method.

公开(公告)号：US12278240B2

公开(公告)日：2025-04-15

申请号：US17750168

申请日：2022-05-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： I-Wen Wang ,  Chia-Chun Wu ,  Hui-Zhong Zhuang ,  Yung-Chen Chien ,  Jerry Chang Jui Kao ,  Xiangdong Chen

IPC: H01L27/00 ,  H01L27/118 ,  G06F30/392

Abstract: An IC device includes first and second power rails extending in a first direction and carrying one of a power supply or reference voltage, a third power rail extending between the first and second power rails and carrying the other of the power supply or reference voltage, and a plurality of transistors including first through fourth active areas extending between the first and second power rails, a plurality of gate structures extending perpendicularly to the first direction, and first and second conductive segments extending in the second direction across the third power rail. Each of the second and third active areas is adjacent to the third power rail, each of the first and second conductive segments is electrically connected to S/D structures in each of the second and third active areas, and the plurality of transistors is configured as one of an AOI, an OAI, or a four-input NAND gate.

公开(公告)号：US12243741B2

公开(公告)日：2025-03-04

申请号：US17674674

申请日：2022-02-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Johnny Chiahao Li ,  Shih-Ming Chang ,  Ken-Hsien Hsieh ,  Chi-Yu Lu ,  Yung-Chen Chien ,  Hui-Zhong Zhuang ,  Jerry Chang Jui Kao ,  Xiangdong Chen

IPC: H01L21/027 ,  H01L21/02 ,  H01L21/306 ,  H01L21/762 ,  H01L23/498 ,  H01L23/522

Abstract: A method includes forming a conductive member over a first conductive line; forming a second conductive line over the conductive member; and removing a portion of the conductive member exposed by the second conductive line to form a conductive via. The formation of the second conductive line is implemented prior to the formation of the conductive via. A semiconductor structure includes a first conductive line having a first surface; a second conductive line disposed above the first conductive line and having a second surface overlapping the first surface; and a conductive via electrically connected to the first surface and the second surface. The conductive via includes a first end disposed within the first surface, a second end disposed within the second surface, and a cross-section between the first end and the second end, wherein at least two of interior angles of the cross-section are substantially unequal to 90°.

公开(公告)号：US12199612B2

公开(公告)日：2025-01-14

申请号：US17858844

申请日：2022-07-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC NANJING COMPANY, LIMITED

Inventor： Xing Chao Yin ,  Huaixin Xian ,  Hui-Zhong Zhuang ,  Yung-Chen Chien ,  Jerry Chang Jui Kao ,  Xiangdong Chen

IPC: H03K3/037 ,  H01L21/8238 ,  H01L27/092 ,  H03K17/687

Abstract: A semiconductor device includes: a cell region including active regions where components of transistors are formed; the cell region are arranged to function as a D flip-flop that includes a primary latch (having a first sleepy inverter and a first non-sleepy (NS) inverter), a secondary latch (having a second sleepy inverter and a second NS inverter), and a clock buffer (having third and fourth NS inverters). The transistors are grouped: a first group has a standard threshold voltage (Vt_std); a second group has a low threshold voltage (Vt_low); and an optional third group has a high threshold voltage (Vt_high). The transistors which comprise the first or second NS inverter have Vt_low. Alternatively, the transistors of the cell region are further arranged to function as a scan-insertion type of D flip-flop (SDFQ) that further includes a multiplexer; and the transistors of the multiplexer have Vt_low.

公开(公告)号：US12125792B2

公开(公告)日：2024-10-22

申请号：US18128742

申请日：2023-03-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jung-Chan Yang ,  Chi-Yu Lu ,  Hui-Zhong Zhuang ,  Chih-Liang Chen

IPC: H01L23/535 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/528 ,  H01L23/538 ,  H01L27/02 ,  H01L29/40 ,  H01L29/417

CPC classification number: H01L23/535 ,  H01L21/76895 ,  H01L21/823475 ,  H01L23/5221 ,  H01L23/528 ,  H01L23/5286 ,  H01L23/5386 ,  H01L27/0207 ,  H01L29/401 ,  H01L29/41725

Abstract: A method of forming a semiconductor device, includes forming an active region; forming first, second and third metal-to-drain/source (MD) contact structures which extend in a first direction, and correspondingly overlap and electrically couple to the active region; forming a via-to-via (V2V) rail which extends in a second direction perpendicular to the first direction, overlaps at least the first MD contact structure and the third MD contact structures; forming a first via-to-MD (VD) structure over, and electrically coupled to, the first MD contact structure and the V2V rail; and forming a first conductive segment which overlaps the V2V rail, is in a first metallization layer, and is electrically coupled to the first VD structure.

公开(公告)号：US12033935B2

公开(公告)日：2024-07-09

申请号：US17836896

申请日：2022-06-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Guo-Huei Wu ,  Hui-Zhong Zhuang ,  Chih-Liang Chen ,  Cheng-Chi Chuang ,  Shang-Wen Chang ,  Yi-Hsun Chiu

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5283

Abstract: A semiconductor device includes a first gate structure extending along a first lateral direction. The semiconductor device includes a first interconnect structure, disposed above the first gate structure, that extends along a second lateral direction perpendicular to the first lateral direction. The first interconnect structure includes a first portion and a second portion electrically isolated from each other by a first dielectric structure. The semiconductor device includes a second interconnect structure, disposed between the first gate structure and the first interconnect structure, that electrically couples the first gate structure to the first portion of the first interconnect structure. The second interconnect structure includes a recessed portion that is substantially aligned with the first gate structure and the dielectric structure along a vertical direction.

公开(公告)号：US20240222269A1

公开(公告)日：2024-07-04

申请号：US18604071

申请日：2024-03-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Guo-Huei Wu ,  Hui-Zhong Zhuang ,  Chih-Liang Chen ,  Cheng-Chi Chuang ,  Shang-Wen Chang ,  Yi-Hsun Chiu

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5283

Abstract: A semiconductor device includes a first gate structure extending along a first lateral direction. The semiconductor device includes a first interconnect structure, disposed above the first gate structure, that extends along a second lateral direction perpendicular to the first lateral direction. The first interconnect structure includes a first portion and a second portion electrically isolated from each other by a first dielectric structure. The semiconductor device includes a second interconnect structure, disposed between the first gate structure and the first interconnect structure, that electrically couples the first gate structure to the first portion of the first interconnect structure. The second interconnect structure includes a recessed portion that is substantially aligned with the first gate structure and the dielectric structure along a vertical direction.

公开(公告)号：US11983479B2

公开(公告)日：2024-05-14

申请号：US17885118

申请日：2022-08-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jung-Chan Yang ,  Ting-Wei Chiang ,  Jerry Chang-Jui Kao ,  Hui-Zhong Zhuang ,  Lee-Chung Lu ,  Li-Chun Tien ,  Meng-Hung Shen ,  Shang-Chih Hsieh ,  Chi-Yu Lu

IPC: G06F30/394 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L27/118

CPC classification number: G06F30/394 ,  H01L23/5226 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11887

Abstract: A method of fabricating an integrated circuit includes placing a first set of conductive feature patterns on a first level, placing a second set of conductive feature patterns on a second level, placing a first set of via patterns between the second set of conductive feature patterns and the first set of conductive feature patterns, placing a third set of conductive feature patterns on a third level different from the first level and the second level, placing a second set of via patterns between the third set of conductive feature patterns and the second set of conductive feature patterns, and manufacturing the integrated circuit based on at least one of the above patterns of the integrated circuit.

公开(公告)号：US11973110B2

公开(公告)日：2024-04-30

申请号：US17313748

申请日：2021-05-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Che-Yuan Chang ,  Hui-Zhong Zhuang ,  Chih-Liang Chen

IPC: H01L29/06 ,  H01L49/02

CPC classification number: H01L29/0653 ,  H01L28/40

Abstract: A semiconductor structure includes a substrate and a first capacitor. The substrate includes an active region. The first capacitor is over the substrate and free from overlapping the active region from a top view perspective.