公开(公告)号：US12261188B2

公开(公告)日：2025-03-25

申请号：US18301714

申请日：2023-04-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Keng-Ying Liao ,  Yu-Chu Lin ,  Chih Wei Sung ,  Shih Sian Wang ,  Chi-Chung Jen ,  Yu-chien Ku ,  Yen-Jou Wu ,  Huai-jen Tung ,  Po-Zen Chen

IPC: H01L27/146

Abstract: A device is disclosed. The device includes a plurality of pixels disposed over a first surface of a semiconductor layer. The device includes a device layer disposed over the first surface. The device includes metallization layers disposed over the device layer. One of the metallization layers, closer to the first surface than any of other ones of the metallization layers, includes at least one conductive structure. The device includes an oxide layer disposed over a second surface of the semiconductor layer, the second surface being opposite to the first surface, the oxide layer also lining a recess that extends through the semiconductor layer. The device includes a spacer layer disposed between inner sidewalls of the recess and the oxide layer. The device includes a pad structure extending through the oxide layer and the device layer to be in physical contact with the at least one conductive structure.

公开(公告)号：US20240404832A1

公开(公告)日：2024-12-05

申请号：US18204995

申请日：2023-06-02

Applicant: Taiwan Semiconductor Manufacturing Company LTD

Inventor： Chenchia Hung ,  Keng-Ying Liao ,  Po-Zen Chen ,  Chih Wei Sung ,  Chien-Chung Chen

IPC: H01L21/306 ,  H01L27/146

Abstract: A method of fabricating a semiconductor structure includes disposing a metal catalyst on a surface of a semiconductor. Thereafter, metal assisted chemical etching is performed, including holding the semiconductor immersed in an etchant solution and catalyzing an etching chemical reaction between the etchant solution and the semiconductor using the metal catalyst to etch the semiconductor to form a channel in the semiconductor. During at least a portion of the metal assisted chemical etching the semiconductor is held immersed in the etchant solution with a surface normal of the surface of the semiconductor at a non-zero angle respective to gravity. In some examples, an orientation of the semiconductor is changed during the metal assisted chemical etching to form the channel in the semiconductor with at least one bend or curved portion.

公开(公告)号：US20210036179A1

公开(公告)日：2021-02-04

申请号：US16865819

申请日：2020-05-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih Wei Sung ,  Chung-Bin Tseng ,  Keng-Ying Liao ,  Yen-Jou Wu ,  Po-Zen Chen ,  Su-Yu Yeh ,  Ching-Chung Su

IPC: H01L31/18

Abstract: A method includes forming image sensors in a semiconductor substrate. A first alignment mark is formed close to a front side of the semiconductor substrate. The method further includes performing a backside polishing process to thin the semiconductor substrate, forming a second alignment mark on the backside of the semiconductor substrate, and forming a feature on the backside of the semiconductor substrate. The feature is formed using the second alignment mark for alignment.

公开(公告)号：US20230253433A1

公开(公告)日：2023-08-10

申请号：US18301714

申请日：2023-04-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Keng-Ying Liao ,  Yu-Chu Lin ,  Chih Wei Sung ,  Shih Sian Wang ,  Chi-Chung Jen ,  Yu-chien Ku ,  Yen-Jou Wu ,  Huai-jen Tung ,  Po-Zen Chen

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/1464 ,  H01L27/14683

Abstract: A device is disclosed. The device includes a plurality of pixels disposed over a first surface of a semiconductor layer. The device includes a device layer disposed over the first surface. The device includes metallization layers disposed over the device layer. One of the metallization layers, closer to the first surface than any of other ones of the metallization layers, includes at least one conductive structure. The device includes an oxide layer disposed over a second surface of the semiconductor layer, the second surface being opposite to the first surface, the oxide layer also lining a recess that extends through the semiconductor layer. The device includes a spacer layer disposed between inner sidewalls of the recess and the oxide layer. The device includes a pad structure extending through the oxide layer and the device layer to be in physical contact with the at least one conductive structure.

公开(公告)号：US20220367559A1

公开(公告)日：2022-11-17

申请号：US17873845

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Keng-Ying Liao ,  Huai-jen Tung ,  Chih Wei Sung ,  Po-Zen Chen ,  Yu-chien Ku ,  Yu-Chu Lin ,  Chi-Chung Jen ,  Yen-Jou Wu ,  Tsun-Kai Tsao ,  Yung-Lung Yang

IPC: H01L27/146

Abstract: A method includes forming a dielectric layer over a first surface of a semiconductor layer, the dielectric layer including a metallization layer. The method includes forming an opening to expose a portion of the dielectric layer. The method includes forming a buffer oxide layer lining the opening. The method includes forming, according to a patternable layer, a recess in the buffer oxide layer partially extending from a second surface of the buffer oxide layer. The method includes removing the patternable layer. The method includes extending the recess through the buffer oxide layer and a portion of the dielectric layer to expose a portion of the metallization layer. The method includes filling the recess with a conductive material to form a pad structure configured to provide electrical connection to the metallization layer.

公开(公告)号：US11430909B2

公开(公告)日：2022-08-30

申请号：US16865819

申请日：2020-05-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih Wei Sung ,  Chung-Bin Tseng ,  Keng-Ying Liao ,  Yen-Jou Wu ,  Po-Zen Chen ,  Su-Yu Yeh ,  Ching-Chung Su

IPC: H01L27/146 ,  H01L31/18 ,  H01L23/544

Abstract: A method includes forming image sensors in a semiconductor substrate. A first alignment mark is formed close to a front side of the semiconductor substrate. The method further includes performing a backside polishing process to thin the semiconductor substrate, forming a second alignment mark on the backside of the semiconductor substrate, and forming a feature on the backside of the semiconductor substrate. The feature is formed using the second alignment mark for alignment.

公开(公告)号：US10658269B2

公开(公告)日：2020-05-19

申请号：US16389762

申请日：2019-04-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Tsung-Han Tsai ,  Volume Chien ,  Yung-Lung Hsu ,  Chung-Bin Tseng ,  Keng-Ying Liao ,  Po-Zen Chen

IPC: H01L21/76 ,  H01L21/331 ,  H01L21/44 ,  H01L23/48 ,  H01L21/768 ,  H01L27/06 ,  H01L27/146

Abstract: The present disclosure provides a semiconductor structure. The structure includes a first substrate; a first dielectric layer having a first surface in proximity to the first substrate and a second surface away from the first substrate; a first interconnect penetrating the first surface of the first dielectric layer; and a protection layer extending along a portion of a sidewall of the first interconnect. A thickness of the protection layer is in a range of from about 0.02 μm to about 0.2 μm.

公开(公告)号：US10269684B2

公开(公告)日：2019-04-23

申请号：US15815392

申请日：2017-11-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Tsung-Han Tsai ,  Volume Chien ,  Yung-Lung Hsu ,  Chung-Bin Tseng ,  Keng-Ying Liao ,  Po-Zen Chen

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L27/06 ,  H01L27/146

Abstract: The present disclosure provides a semiconductor structure. The structure includes a first substrate; a first dielectric layer having a first surface in proximity to the first substrate and a second surface away from the first substrate; a first interconnect penetrating the first surface of the first dielectric layer; and a protection layer extending along a portion of a sidewall of the first interconnect. A thickness of the protection layer is in a range of from about 0.02 μm to about 0.2 μm.

公开(公告)号：US10056316B2

公开(公告)日：2018-08-21

申请号：US15823297

申请日：2017-11-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Tsung-Han Tsai ,  Volume Chien ,  Yung-Lung Hsu ,  Chung-Bin Tseng ,  Keng-Ying Liao ,  Po-Zen Chen

IPC: H01L21/44 ,  H01L23/48 ,  H01L21/768 ,  H01L27/06 ,  H01L27/146

CPC classification number: H01L23/481 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76898 ,  H01L27/0688 ,  H01L27/14634 ,  H01L2224/24147 ,  H01L2224/8203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure provides a semiconductor structure. The structure includes a first substrate; a first dielectric layer having a first surface in proximity to the first substrate and a second surface away from the first substrate; a first interconnect penetrating the first surface of the first dielectric layer; and a protection layer extending along a portion of a sidewall of the first interconnect. A thickness of the protection layer is in a range of from about 0.02 μm to about 0.2 μm.

公开(公告)号：US10008530B2

公开(公告)日：2018-06-26

申请号：US14610049

申请日：2015-01-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Keng-Ying Liao ,  Chung-Bin Tseng ,  Cheng-Hsien Chou ,  Jiech-Fun Lu ,  Po-Zen Chen ,  Yi-Hung Chen

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14623 ,  H01L27/14636 ,  H01L27/1464

Abstract: Some embodiments of the present disclosure provide a back side illuminated (BSI) image sensor. The BSI image sensor includes a semiconductive substrate, a deep trench isolation (DTI) at a back side of the semiconductive substrate, and a dielectric layer. the dielectric layer includes a top portion over the back side, and a side portion lined to a sidewall of the DTI. The BSI image sensor includes a planarization stop layer disposed conformally on top of the dielectric layer. The planarization stop layer includes a top section on the top portion, a side section lined against the side portion, and a first transmittance. The BSI image sensor includes a low-transparent material inside the DTI, and the low-transparent material includes a second transmittance. The second transmittance is lower than the first transmittance.