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    SYSTEM ON CHIP FIREWALL MEMORY ARCHITECTURE
    1.
    发明申请
    SYSTEM ON CHIP FIREWALL MEMORY ARCHITECTURE 有权

    公开(公告)号：US20240380731A1

    公开(公告)日：2024-11-14

    申请号：US18783999

    申请日：2024-07-25

    Applicant: Texas Instruments Incorporated

    Inventor： Amritpal Singh Mundra ,  Chunhua Hu

    IPC: H04L9/40 ,  G06F21/71 ,  G06F21/76 ,  G06F21/85

    Abstract: Systems and methods provide unified control of firewalls of functional units distributed throughout a system-on-a-chip (SoC) using a configuration controller and security bus. Such unified control enables configuration of a memory to provide a unified view configuration memories of the firewalls, regardless of the locations of the firewalls in the SoC. An example system providing such control includes multiple functional units including multiple firewalls, respectively, in which each firewall stores configuration data for a corresponding functional unit of the functional units; a first bus coupled to the functional units; a second bus that is coupled to the functional units and is electrically isolated from the first bus; and a configuration controller coupled to the second bus and configured to use the second bus to control the configuration data that is stored in each of the firewalls.

    Secure message routing
    7.
    发明授权
    Secure message routing 有权

    公开(公告)号：US11972030B2

    公开(公告)日：2024-04-30

    申请号：US17402693

    申请日：2021-08-16

    Applicant: Texas Instruments Incorporated

    Inventor： Amritpal Singh Mundra ,  Eric Lasmana

    IPC: G06F21/72 ,  G06F9/54 ,  G06F15/78 ,  G06F21/74

    CPC classification number: G06F21/72 ,  G06F9/546 ,  G06F15/7807 ,  G06F21/74

    Abstract: In described examples, a method of routing messages in a system on a chip (SoC) includes a secure message router receiving a message including a content, an identifier of the message's sending (origin) functional block and/or of a receiving (destination) functional block, a message secure value, a promote value, and a demote value. A context corresponding to the identifier is retrieved from a memory. The context includes an allow promote value and an allow demote value. The message secure value is increased if the promote value requests the increase and matches the allow promote value. The message secure value is decreased if the demote value requests the decrease and matches the allow demote value. Cleartext corresponding to the content is made accessible by the destination if the context secure value matches the message secure value. The message is then outputted from the secure message router to the destination.

    Flexible hybrid firewall architecture
    8.
    发明授权
    Flexible hybrid firewall architecture 有权

    公开(公告)号：US11212256B2

    公开(公告)日：2021-12-28

    申请号：US16786734

    申请日：2020-02-10

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Amritpal Singh Mundra ,  Brian J. Karguth ,  Timothy Anderson ,  Kai Chirca ,  Charles Fuoco

    IPC: H04L29/06

    Abstract: A flexible hybrid firewall architecture is disclosed. A system implementing such an architecture includes an access control register, a memory having at least a region to which access is controllable by the access control register, the access control register including first field that contains a privilege identifier (ID) and a plurality of additional fields, each additional field containing control bits corresponding to a respective one of a plurality of permission levels, and control circuitry that, in response to receiving a transaction containing a transaction privilege ID, a security indicator, and a privilege indicator, controls access to the region when the transaction privilege ID matches the privilege ID contained in the first field by using the control bits of a field of the additional fields that corresponds to a security level indicated by the security indicator and a privilege level indicated by the privilege indicator of the transaction.

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