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    POWER CONVERTER HAVING A CONDUCTIVE CLIP
    1.
    发明申请
    POWER CONVERTER HAVING A CONDUCTIVE CLIP 审中-公开

    公开(公告)号：US20190287885A1

    公开(公告)日：2019-09-19

    申请号：US15925191

    申请日：2018-03-19

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Rajeev Dinkar Joshi ,  Jie Mao

    IPC: H01L23/495 ,  H01L23/492 ,  H01L23/64 ,  H01L23/00

    Abstract: A power supply module includes a metallic clip including a plate having an area and a first and a second ridge on opposite sides of the plate. The ridges bent in the same direction away from the plate. The first and the second ridges conductively attached to the substrate, where the substrate is of insulating material integral with metal traces, the plate roofing over the substrate between the ridges. A first MOS field-effect transistor (FET) chip and, horizontally side-by-side, a second MOSFET chip are attached and wire bonded to the substrate under the plate. The drain of the first MOSFET is connected to the input terminal of the module, the source of the first MOSFET is tied to the drain of the second MOSFET, and the source of the second MOSFET, together with the second ridge, is connected to ground. A driver and controller chip is attached to the substrate under the plate and wire bonded to the gates of the first and second MOSFET. A capacitor is attached to the substrate under the clip plate and conductively connected to the first clip ridge and to the drain of the first MOSFET.

    Power converter having a conductive clip
    3.
    发明授权
    Power converter having a conductive clip 有权

    公开(公告)号：US10573585B2

    公开(公告)日：2020-02-25

    申请号：US15925191

    申请日：2018-03-19

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Rajeev Dinkar Joshi ,  Jie Mao

    IPC: H01L23/495 ,  H01L23/64 ,  H01L23/00 ,  H01L23/492

    Abstract: A power supply module includes a metallic clip including a plate having an area and a first and a second ridge on opposite sides of the plate. The ridges bent in the same direction away from the plate. The first and the second ridges conductively attached to the substrate, where the substrate is of insulating material integral with metal traces, the plate roofing over the substrate between the ridges. A first MOS field-effect transistor (FET) chip and, horizontally side-by-side, a second MOSFET chip are attached and wire bonded to the substrate under the plate. The drain of the first MOSFET is connected to the input terminal of the module, the source of the first MOSFET is tied to the drain of the second MOSFET, and the source of the second MOSFET, together with the second ridge, is connected to ground. A driver and controller chip is attached to the substrate under the plate and wire bonded to the gates of the first and second MOSFET. A capacitor is attached to the substrate under the clip plate and conductively connected to the first clip ridge and to the drain of the first MOSFET.

    OPEN CAVITY PACKAGE USING CHIP-EMBEDDING TECHNOLOGY
    4.
    发明申请
    OPEN CAVITY PACKAGE USING CHIP-EMBEDDING TECHNOLOGY 有权
    使用芯片嵌入技术的开放封装

    公开(公告)号：US20170015548A1

    公开(公告)日：2017-01-19

    申请号：US14963362

    申请日：2015-12-09

    Applicant: Texas Instruments Incorporated

    Inventor： Jie Mao ,  Hau Nguyen ,  Luu Nguyen ,  Anindya Poddar

    IPC: B81C1/00 ,  B81B7/00

    CPC classification number: B81C1/00873 ,  B81B7/007 ,  B81B2201/0214 ,  B81B2201/0235 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81B2201/0278 ,  B81B2201/0292 ,  B81B2201/047 ,  B81B2207/07 ,  B81B2207/098 ,  B81C1/00333 ,  B81C2201/0125 ,  B81C2201/0132 ,  B81C2201/0159 ,  B81C2201/0181 ,  B81C2201/0188 ,  B81C2203/0136 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/3121 ,  H01L24/19 ,  H01L2221/68359 ,  H01L2224/04105 ,  H01L2224/96 ,  H01L2924/3511

    Abstract: A method for fabricating packaged semiconductor devices (100) with an open cavity (110a) in panel format; placing (process 201) on an adhesive carrier tape a panel-sized grid of metallic pieces having a flat pad (230) and symmetrically placed vertical pillars (231); attaching (process 202) semiconductor chips (101) with sensor systems face-down onto the tape; laminating (process 203) and thinning (process 204) low CTE insulating material (234) to fill gaps between chips and grid; turning over (process 205) assembly to remove tape; plasma-cleaning assembly front side, sputtering and patterning (process 206) uniform metal layer across assembly and optionally plating (process 209) metal layer to form rerouting traces and extended contact pads for assembly; laminating (process 212) insulating stiffener across panel; opening (process 213) cavities in stiffener to access the sensor system; and singulating (process 214) packaged devices by cutting metallic pieces.

    Abstract translation: 一种以面板格式制造具有开口腔（110a）的封装半导体器件（100）的方法; 将具有平垫（230）和对称放置的垂直柱（231）的金属片的面板尺寸网格放置（处理201）在粘合剂载带上。 将具有传感器系统的半导体芯片（工艺202）面朝下地附接到带上; 层压（工艺203）和减薄（工艺204）低CTE绝缘材料（234）以填充芯片和网格之间的间隙; 翻转（过程205）组装以去除胶带; 等离子体清洁组件正面，溅射和图案化（工艺206）跨组合均匀的金属层和任选的电镀（工艺209）金属层以形成重新布线迹线和扩展的接触垫用于组装; 层压（工艺212）跨板的绝缘加强件; 在加强件中打开（过程213）空腔以接近传感器系统; 并通过切割金属片来分割（处理214）包装的装置。

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