公开(公告)号：US10573585B2

公开(公告)日：2020-02-25

申请号：US15925191

申请日：2018-03-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rajeev Dinkar Joshi ,  Jie Mao

IPC: H01L23/495 ,  H01L23/64 ,  H01L23/00 ,  H01L23/492

Abstract: A power supply module includes a metallic clip including a plate having an area and a first and a second ridge on opposite sides of the plate. The ridges bent in the same direction away from the plate. The first and the second ridges conductively attached to the substrate, where the substrate is of insulating material integral with metal traces, the plate roofing over the substrate between the ridges. A first MOS field-effect transistor (FET) chip and, horizontally side-by-side, a second MOSFET chip are attached and wire bonded to the substrate under the plate. The drain of the first MOSFET is connected to the input terminal of the module, the source of the first MOSFET is tied to the drain of the second MOSFET, and the source of the second MOSFET, together with the second ridge, is connected to ground. A driver and controller chip is attached to the substrate under the plate and wire bonded to the gates of the first and second MOSFET. A capacitor is attached to the substrate under the clip plate and conductively connected to the first clip ridge and to the drain of the first MOSFET.

公开(公告)号：US09355946B2

公开(公告)日：2016-05-31

申请号：US14823487

申请日：2015-08-11

Applicant: Texas Instruments Incorporated

Inventor： Rajeev Dinkar Joshi

IPC: H01L23/495 ,  H01L25/16 ,  H01L25/00 ,  H02M7/00 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L23/49575 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/49531 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49838 ,  H01L23/49861 ,  H01L25/165 ,  H01L25/50 ,  H02M7/003

Abstract: Power supply system comprises vertically sequentially a QFN leadframe, a first chip with FET terminals on opposite sides, a flat interposer, and a second chip with FET terminals and the terminals of the integrated driver-and-control circuit on a single side. Leadframe pad has a portion recessed as pocket with a depth and an outline suitable for attaching the first chip with one terminal in the pocket and the opposite terminal co-planar with the un-recessed pad surface. The interposer comprises metal patterned in traces separated by gaps; the traces include metal of a first height and metal of a second height smaller than the first height, and insulating material filling the gaps and the height differences; one interposer side attached to the leadframe pad with the first chip, the opposite interposer side attached to the terminals of the second chip.

Abstract translation: 电源系统包括垂直顺序地包括QFN引线框，具有相对侧的FET端子的第一芯片，平面插入器，以及具有FET端子的第二芯片和集成驱动器和控制电路的端子。 引线框垫具有凹陷的凹部，其深度和轮廓适合于将第一芯片与一个端子连接在凹槽中，而相对的端子与未凹陷的垫表面共面。 插入器包括由间隙分隔的痕迹图案化的痕迹; 迹线包括第一高度的金属和小于第一高度的第二高度的金属，以及填充间隙和高度差的绝缘材料; 一个插入器侧用第一芯片附接到引线框架焊盘，相对的插入器侧连接到第二芯片的端子。

公开(公告)号：US10734313B2

公开(公告)日：2020-08-04

申请号：US15951021

申请日：2018-04-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jeffrey Morroni ,  Rajeev Dinkar Joshi ,  Sreenivasan K. Koduri ,  Sujan Kundapur Manohar ,  Yogesh K. Ramadass ,  Anindya Poddar

IPC: H01L23/495 ,  H01L25/065 ,  H01L23/31 ,  H01L23/29 ,  H01L23/498 ,  H01L25/16 ,  H01L23/50

Abstract: A semiconductor package includes a leadframe and a semiconductor die attached to the leadframe by way of solder posts. In a stacked arrangement, the package also includes a passive component disposed between the leadframe and the semiconductor die and electrically connected to the semiconductor die through the leadframe.

公开(公告)号：US09468087B1

公开(公告)日：2016-10-11

申请号：US14797510

申请日：2015-07-13

Applicant: Texas Instruments Incorporated

Inventor： Rajeev Dinkar Joshi

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L23/02 ,  H01L23/10 ,  H01L23/34 ,  H01L21/76 ,  H05K1/02 ,  H02M7/00 ,  H05K1/18 ,  H05K7/20 ,  H05K3/34

CPC classification number: H05K1/0204 ,  H01L23/4334 ,  H01L23/49531 ,  H01L23/49562 ,  H01L23/49575 ,  H01L2224/48137 ,  H01L2224/48247 ,  H02M7/003 ,  H05K1/0209 ,  H05K1/181 ,  H05K7/205 ,  H05K2201/066 ,  H05K2201/10166 ,  H05K2201/10689 ,  Y02P70/611

Abstract: Disclosed examples include power modules and fabrication methods therefor in which one or more power device dies include a switching device and a second device die with a circuit component are mounted to a lead frame or other interconnect structure on a substrate structure, and a body structure is formed around portions of the power module providing a first opening to expose a portion of the substrate structure to provide an externally accessible first exposed surface along the top of the power module, and the body structure includes a second opening exposing a portion of the first device die along the bottom of the power module to provide a thermally conductive path to draw heat away from the power device dies.

Abstract translation: 公开的实例包括其中一个或多个功率器件管芯包括开关器件的功率模块及其制造方法，并且具有电路部件的第二器件裸片安装到衬底结构上的引线框架或其他互连结构，并且主体结构 形成在功率模块的周围的部分上，提供第一开口以暴露基板结构的一部分，以沿着功率模块的顶部提供外部可接近的第一暴露表面，并且主体结构包括第二开口，暴露第一器件的一部分 沿着功率模块的底部模制，以提供导热路径，以将热量从功率器件裸片吸取。

公开(公告)号：US20190287885A1

公开(公告)日：2019-09-19

申请号：US15925191

申请日：2018-03-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rajeev Dinkar Joshi ,  Jie Mao

IPC: H01L23/495 ,  H01L23/492 ,  H01L23/64 ,  H01L23/00

Abstract: A power supply module includes a metallic clip including a plate having an area and a first and a second ridge on opposite sides of the plate. The ridges bent in the same direction away from the plate. The first and the second ridges conductively attached to the substrate, where the substrate is of insulating material integral with metal traces, the plate roofing over the substrate between the ridges. A first MOS field-effect transistor (FET) chip and, horizontally side-by-side, a second MOSFET chip are attached and wire bonded to the substrate under the plate. The drain of the first MOSFET is connected to the input terminal of the module, the source of the first MOSFET is tied to the drain of the second MOSFET, and the source of the second MOSFET, together with the second ridge, is connected to ground. A driver and controller chip is attached to the substrate under the plate and wire bonded to the gates of the first and second MOSFET. A capacitor is attached to the substrate under the clip plate and conductively connected to the first clip ridge and to the drain of the first MOSFET.

公开(公告)号：US11430722B2

公开(公告)日：2022-08-30

申请号：US15951003

申请日：2018-04-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jeffrey Morroni ,  Rajeev Dinkar Joshi ,  Sreenivasan K. Koduri ,  Sujan Kundapur Manohar ,  Yogesh K. Ramadass ,  Anindya Poddar

IPC: H01L23/00 ,  H01L23/495 ,  H01L23/498 ,  H01L21/48 ,  H01L23/50

Abstract: A semiconductor package includes a leadframe, a semiconductor die attached to the leadframe, and a passive component electrically connected to the semiconductor die through the leadframe. The leadframe includes a cavity in a side of the leadframe opposite the semiconductor die, and at least a portion of the passive component resides within the cavity in a stacked arrangement.

公开(公告)号：US20150348890A1

公开(公告)日：2015-12-03

申请号：US14823487

申请日：2015-08-11

Applicant: Texas Instruments Incorporated

Inventor： Rajeev Dinkar Joshi

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/498 ,  H01L25/16

CPC classification number: H01L23/49575 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/49531 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49838 ,  H01L23/49861 ,  H01L25/165 ,  H01L25/50 ,  H02M7/003

Abstract: Power supply system comprises vertically sequentially a QFN leadframe, a first chip with FET terminals on opposite sides, a flat interposer, and a second chip with FET terminals and the terminals of the integrated driver-and-control circuit on a single side. Leadframe pad has a portion recessed as pocket with a depth and an outline suitable for attaching the first chip with one terminal in the pocket and the opposite terminal co-planar with the un-recessed pad surface. The interposer comprises metal patterned in traces separated by gaps; the traces include metal of a first height and metal of a second height smaller than the first height, and insulating material filling the gaps and the height differences; one interposer side attached to the leadframe pad with the first chip, the opposite interposer side attached to the terminals of the second chip.

Abstract translation: 电源系统包括垂直顺序地包括QFN引线框，具有相对侧的FET端子的第一芯片，平面插入器，以及具有FET端子的第二芯片和集成驱动器和控制电路的端子。 引线框垫具有凹陷的凹部，其深度和轮廓适合于将第一芯片与一个端子连接在凹槽中，而相对的端子与未凹陷的垫表面共面。 插入器包括由间隙分隔的痕迹图案化的痕迹; 迹线包括第一高度的金属和小于第一高度的第二高度的金属，以及填充间隙和高度差的绝缘材料; 一个插入器侧用第一芯片附接到引线框架焊盘，相对的插入器侧连接到第二芯片的端子。

公开(公告)号：US09136256B2

公开(公告)日：2015-09-15

申请号：US14185502

申请日：2014-02-20

Applicant: Texas Instruments Incorporated

Inventor： Rajeev Dinkar Joshi

IPC: H01L21/44 ,  H01L25/16 ,  H01L25/00 ,  H01L23/495 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31 ,  H02M7/00

CPC classification number: H01L23/49575 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/49531 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49838 ,  H01L23/49861 ,  H01L25/165 ,  H01L25/50 ,  H02M7/003

Abstract: Power supply system (100) comprises vertically sequentially a QFN leadframe (101), a first chip (110) with FET terminals on opposite sides, a flat interposer (120), and a second chip (130) with FET terminals and the terminals of the integrated driver-and-control circuit on a single side. Leadframe pad (107) has a portion (107a) recessed as pocket with a depth and an outline suitable for attaching the first chip with one terminal in the pocket and the opposite terminal co-planar with the un-recessed pad surface. The interposer comprises metal patterned in traces separated by gaps; the traces include metal of a first height and metal of a second height smaller than the first height, and insulating material filling the gaps and the height differences; one interposer side attached to the leadframe pad with the first chip, the opposite interposer side attached to the terminals of the second chip.

Abstract translation: 电源系统（100）包括垂直顺序地包括QFN引线框架（101），具有相对侧的FET端子的第一芯片（110），平面插入器（120）和具有FET端子的第二芯片（130） 集成的驱动和控制电路在一侧。 引线框架（107）具有作为凹槽凹陷的部分（107a），其深度和轮廓适合于将第一芯片与一个端子连接在凹槽中，而相对端子与未凹陷的焊盘表面共面。 插入器包括由间隙分隔的痕迹图案化的痕迹; 迹线包括第一高度的金属和小于第一高度的第二高度的金属，以及填充间隙和高度差的绝缘材料; 一个插入器侧用第一芯片附接到引线框架焊盘，相对的插入器侧连接到第二芯片的端子。

公开(公告)号：US20150235999A1

公开(公告)日：2015-08-20

申请号：US14185502

申请日：2014-02-20

Applicant: Texas Instruments Incorporated

Inventor： Rajeev Dinkar Joshi

IPC: H01L25/16 ,  H01L23/495 ,  H02M7/00 ,  H01L21/56 ,  H01L23/31 ,  H01L25/00 ,  H01L23/498

CPC classification number: H01L23/49575 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/49531 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49838 ,  H01L23/49861 ,  H01L25/165 ,  H01L25/50 ,  H02M7/003

Abstract: Power supply system (100) comprises vertically sequentially a QFN leadframe (101), a first chip (110) with FET terminals on opposite sides, a flat interposer (120), and a second chip (130) with FET terminals and the terminals of the integrated driver-and-control circuit on a single side. Leadframe pad (107) has a portion (107a) recessed as pocket with a depth and an outline suitable for attaching the first chip with one terminal in the pocket and the opposite terminal co-planar with the un-recessed pad surface. The interposer comprises metal patterned in traces separated by gaps; the traces include metal of a first height and metal of a second height smaller than the first height, and insulating material filling the gaps and the height differences; one interposer side attached to the leadframe pad with the first chip, the opposite interposer side attached to the terminals of the second chip.

Abstract translation: 电源系统（100）包括垂直顺序地包括QFN引线框架（101），具有相对侧的FET端子的第一芯片（110），平面插入器（120）和具有FET端子的第二芯片（130） 集成的驱动和控制电路在一侧。 引线框架（107）具有作为凹槽凹陷的部分（107a），其深度和轮廓适合于将第一芯片与一个端子连接在凹槽中，而相对端子与未凹陷的焊盘表面共面。 插入器包括由间隙分隔的痕迹图案化的痕迹; 迹线包括第一高度的金属和小于第一高度的第二高度的金属，以及填充间隙和高度差的绝缘材料; 一个插入器侧用第一芯片附接到引线框架焊盘，相对的插入器侧连接到第二芯片的端子。