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    DIFFERENTIAL PLATE LINE SCREEN TEST FOR FERROELECTRIC LATCH CIRCUITS
    2.
    发明申请
    DIFFERENTIAL PLATE LINE SCREEN TEST FOR FERROELECTRIC LATCH CIRCUITS 有权
    用于电磁绞线电路的差分线路屏蔽测试

    公开(公告)号：US20130021833A1

    公开(公告)日：2013-01-24

    申请号：US13626531

    申请日：2012-09-25

    Applicant: Texas Instruments Incorporated

    Inventor： Scott R. Summerfelt ,  John Anthony Rodriguez ,  Hugh P. McAdams ,  Steven Craig Bartling

    IPC: G11C11/22

    CPC classification number: G11C29/50 ,  G11C11/22

    Abstract: Non-volatile latch circuits, such as in memory cells and flip-flops, that are constructed for reliability screening. The non-volatile latch circuits each include ferroelectric capacitors coupled to storage nodes, for example at the outputs of cross-coupled inverters. Separate plate lines are connected to the ferroelectric capacitors of the complementary storage nodes. A time-zero test of the latch stability margin is performed by setting a logic state at the storage nodes, then programming the state into the ferroelectric capacitors by polarization. After power-down, the plate lines are biased with a differential voltage relative to one another, and the latch is then powered up to attempt recall of the programmed state. The differential voltage disturbs the recall, and provides a measure of the cell margin and its later-life reliability.

    Abstract translation: 构建用于可靠性筛选的非易失性锁存电路，例如在存储器单元和触发器中。 非易失性锁存电路各自包括耦合到存储节点的铁电电容器，例如在交叉耦合的反相器的输出端。 单独的板线连接到互补存储节点的铁电电容器。 通过在存储节点设置逻辑状态，然后通过极化将状态编程到铁电电容器中来执行锁存稳定裕度的时间零测试。 掉电后，电路板以相对于彼此的差分电压偏置，然后锁存器上电以尝试调用编程状态。 差分电压会干扰召回，并提供信号余量的测量及其后期寿命的可靠性。

    Random Number Generation with Ferroelectric Random Access Memory
    4.
    发明申请
    Random Number Generation with Ferroelectric Random Access Memory 审中-公开
    随机数生成与铁电随机存取存储器

    公开(公告)号：US20150355886A1

    公开(公告)日：2015-12-10

    申请号：US14301307

    申请日：2014-06-10

    Applicant: Texas Instruments Incorporated

    Inventor： Eric Thierry Peeters ,  William Francis Kraus ,  Manuel Gilberto Aguilar ,  John Anthony Rodriguez

    IPC: G06F7/58 ,  G11C11/22

    CPC classification number: G06F7/588 ,  G11C7/20 ,  G11C11/225 ,  G11C29/04 ,  G11C2029/4402

    Abstract: A system on chip (SoC) may include a nonvolatile ferroelectric random access memory (FRAM). A random number may be created by applying operating power to the ferroelectric random access memory (FRAM) device and reading a sequence of virgin memory locations within the FRAM device to produce the random number sequence. The sequence of virgin memory locations had previously never been written. The random number may be produced during an initial boot of the SoC, for example. Alternatively, the random number may be saved by a test station during testing of the FRAM device after fabrication of the FRAM device. A memory test of the FRAM may then be performed, after which the random number may be stored in a defined location in the FRAM.

    Abstract translation: 片上系统（SoC）可以包括非易失性铁电随机存取存储器（FRAM）。 可以通过向铁电随机存取存储器（FRAM）装置施加操作功率并读取FRAM装置内的一系列原始存储器位置来产生随机数序列来产生随机数。 以前从未写过处女记忆位置的顺序。 例如，可以在SoC的初始引导期间产生随机数。 或者，在FRAM设备制造之后，在测试FRAM设备期间，随机数可由测试台保存。 然后可以执行FRAM的存储器测试，之后可以将随机数存储在FRAM中的定义的位置。

    Physical Unclonable Function System and Method
    5.
    发明申请
    Physical Unclonable Function System and Method 审中-公开

    公开(公告)号：US20190252016A1

    公开(公告)日：2019-08-15

    申请号：US15967511

    申请日：2018-04-30

    Applicant: Texas Instruments Incorporated

    Inventor： John Anthony Rodriguez ,  Richard Allen Bailey

    IPC: G11C11/22 ,  H04L9/32

    CPC classification number: G11C11/2275 ,  G11C11/221 ,  G11C11/2273 ,  H04L9/3278

    Abstract: A method of generating a random number from an electronic circuit memory and/or a system with the electronic circuit memory. The memory comprises a block of ferroelectric two transistor, two capacitor (2T-2C), memory cells. The method comprises: (i) first, writing a predetermined programming pattern to the block cells in a one transistor, one-capacitor (1T-1C) mode, thusly writing, per cell, a same data state to both a first and second sub-cell of the cell; (ii) second, reading the cells in a 2T-2C mode to generate a random number comprising a random bit from each of the cells; (iii) third, restoring the random number into the cells in a 2T-2C mode, thusly writing, per cell, a complementary data state to both a first and second sub-cell of the cell, responsive to a respective random number bit; and fourth, imprinting the random number in each cell in the block.

    Fusible link cell with dual bit storage
    7.
    发明授权
    Fusible link cell with dual bit storage 有权

    公开(公告)号：US10153053B2

    公开(公告)日：2018-12-11

    申请号：US15787905

    申请日：2017-10-19

    Applicant: Texas Instruments Incorporated

    Inventor： Sunil Kumar Dusa ,  Richard Allen Bailey ,  Archana Venugopal ,  John Anthony Rodriguez ,  Michael Allen Ball

    IPC: G11C17/18 ,  G11C17/16

    Abstract: A fuse-programmable register or memory location having a plurality of fusible links of differing electrical characteristics in parallel. In one embodiment, three fusible links with different resistances are provided, such that application of a programming voltage non-uniformly distributes the current among the links, allowing varying voltages to selectively blow one or more of the links. Sensing of the programmed state is performed by applying a voltage across the parallel links and measuring the current in comparison with a plurality of reference currents. Reduction in the overhead chip area per bit and in the serial data communication latency are obtained.

    FUSIBLE LINK CELL WITH DUAL BIT STORAGE
    8.
    发明申请
    FUSIBLE LINK CELL WITH DUAL BIT STORAGE 审中-公开

    公开(公告)号：US20180040381A1

    公开(公告)日：2018-02-08

    申请号：US15787905

    申请日：2017-10-19

    Applicant: Texas Instruments Incorporated

    Inventor： Sunil Kumar Dusa ,  Richard Allen Bailey ,  Archana Venugopal ,  John Anthony Rodriguez ,  Michael Allen Ball

    IPC: G11C17/18 ,  G11C17/16

    CPC classification number: G11C17/18 ,  G11C17/165

    Abstract: A fuse-programmable register or memory location having a plurality of fusible links of differing electrical characteristics in parallel. In one embodiment, three fusible links with different resistances are provided, such that application of a programming voltage non-uniformly distributes the current among the links, allowing varying voltages to selectively blow one or more of the links. Sensing of the programmed state is performed by applying a voltage across the parallel links and measuring the current in comparison with a plurality of reference currents. Reduction in the overhead chip area per bit and in the serial data communication latency are obtained.

    Fusible Link Cell with Dual Bit Storage
    9.
    发明申请
    Fusible Link Cell with Dual Bit Storage 有权
    具有双位存储的可熔链路单元

    公开(公告)号：US20170018311A1

    公开(公告)日：2017-01-19

    申请号：US15146049

    申请日：2016-05-04

    Applicant: Texas Instruments Incorporated

    Inventor： Sunil Kumar Dusa ,  Richard Allen Bailey ,  Archana Venugopal ,  John Anthony Rodriguez ,  Michael Allen Ball

    IPC: G11C17/18 ,  G11C17/16

    CPC classification number: G11C17/18 ,  G11C17/165

    Abstract: A fuse-programmable register or memory location having a plurality of fusible links of differing electrical characteristics in parallel. In one embodiment, three fusible links with different resistances are provided, such that application of a programming voltage non-uniformly distributes the current among the links, allowing varying voltages to selectively blow one or more of the links. Sensing of the programmed state is performed by applying a voltage across the parallel links and measuring the current in comparison with a plurality of reference currents. Reduction in the overhead chip area per bit and in the serial data communication latency are obtained.

    Abstract translation: 熔丝可编程寄存器或存储器位置具有并联的具有不同电特性的多个可熔链路。 在一个实施例中，提供具有不同电阻的三个可熔链路，使得编程电压的施加不均匀地分布在链路之间的电流，允许变化的电压选择性地吹送一个或多个链路。 通过跨多个并联链路施加电压并且与多个参考电流相比测量电流来执行编程状态的感测。 获得每位开销芯片面积的减少和串行数据通信延迟。

    Differential plate line screen test for ferroelectric latch circuits
    10.
    发明授权
    Differential plate line screen test for ferroelectric latch circuits 有权

    公开(公告)号：US08472236B2

    公开(公告)日：2013-06-25

    申请号：US13626531

    申请日：2012-09-25

    Applicant: Texas Instruments Incorporated

    Inventor： Scott R. Summerfelt ,  John Anthony Rodriguez ,  Hugh P. McAdams ,  Steven Craig Bartling

    IPC: G11C11/22

    CPC classification number: G11C29/50 ,  G11C11/22

    Abstract: Non-volatile latch circuits, such as in memory cells and flip-flops, that are constructed for reliability screening. The non-volatile latch circuits each include ferroelectric capacitors coupled to storage nodes, for example at the outputs of cross-coupled inverters. Separate plate lines are connected to the ferroelectric capacitors of the complementary storage nodes. A time-zero test of the latch stability margin is performed by setting a logic state at the storage nodes, then programming the state into the ferroelectric capacitors by polarization. After power-down, the plate lines are biased with a differential voltage relative to one another, and the latch is then powered up to attempt recall of the programmed state. The differential voltage disturbs the recall, and provides a measure of the cell margin and its later-life reliability.

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