公开(公告)号：US11616011B2

公开(公告)日：2023-03-28

申请号：US17360183

申请日：2021-06-28

Applicant: Texas Instruments Incorporated

Inventor： Mona M. Eissa ,  Umamaheswari Aghoram ,  Pushpa Mahalingam ,  Erich Wesley Kinder ,  Bhaskar Srinivasan ,  Brian E. Goodlin

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/768

Abstract: An integrated circuit (IC) includes a semiconductor surface layer of a substrate including circuitry formed in the semiconductor surface layer configured together with a Metal-Insulator-Metal (MIM) capacitor. A multi-layer metal stack on the semiconductor surface layer includes a bottom plate contact metal layer including a bottom capacitor plate contact. A first interlevel dielectric (ILD) layer is over the bottom plate contact metal layer. The MIM capacitor includes a trench in the first ILD layer over the bottom capacitor plate contact, wherein the trench is lined by a bottom capacitor plate with a capacitor dielectric layer thereon, and a top capacitor plate on the capacitor dielectric layer. A fill material fills the trench to form a filled trench. A second ILD layer is over the filled trench. A filled via through the second ILD layer provides a connection to the top capacitor plate.

公开(公告)号：US20210233903A1

公开(公告)日：2021-07-29

申请号：US17228631

申请日：2021-04-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mona M. Eissa ,  Mark R. Kimmich ,  Sudtida Lavangkul ,  Sopa Chevacharoenkul ,  Mark L. Jenson

IPC: H01L27/06 ,  G01R33/04 ,  G01R33/05

Abstract: An integrated circuit has a substrate, a circuit, a core structure, a first encapsulation layer, a second encapsulation layer, and an oxide layer. The circuit includes transistors with active regions developed on the substrate and a metal layer formed above the active regions to provide interconnections for the transistors. The core structure is formed above the metal layer. The first encapsulation layer covers the core structure, and it has a first thermal expansion coefficient. The second encapsulation layer covers the first encapsulation layer over the core structure, and it has a second thermal expansion coefficient that is different from the first thermal expansion coefficient. As a part of the stress relief structure, the oxide layer is formed above the second encapsulation layer. The oxide layer includes an oxide thickness sufficient to mitigate a thermal stress between the first and second encapsulation layers.

公开(公告)号：US20210074630A1

公开(公告)日：2021-03-11

申请号：US16564849

申请日：2019-09-09

Applicant: Texas Instruments Incorporated

Inventor： Mona M. Eissa ,  Umamaheswari Aghoram ,  Pushpa Mahalingam ,  Erich Wesley Kinder ,  Bhaskar Srinivasan ,  Brian E. Goodlin

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/768

Abstract: An integrated circuit (IC) includes a semiconductor surface layer of a substrate including circuitry formed in the semiconductor surface layer configured together with a Metal-Insulator-Metal (MIM) capacitor. A multi-layer metal stack on the semiconductor surface layer includes a bottom plate contact metal layer including a bottom capacitor plate contact. A first interlevel dielectric (ILD) layer is over the bottom plate contact metal layer. The MIM capacitor includes a trench in the first ILD layer over the bottom capacitor plate contact, wherein the trench is lined by a bottom capacitor plate with a capacitor dielectric layer thereon, and a top capacitor plate on the capacitor dielectric layer. A fill material fills the trench to form a filled trench. A second ILD layer is over including the filled trench. A filled via through the second ILD layer provides a contact to a top plate contact on the top capacitor plate.

公开(公告)号：US20170213956A1

公开(公告)日：2017-07-27

申请号：US15003856

申请日：2016-01-22

Applicant: Texas Instruments Incorporated

Inventor： Mona M. Eissa ,  Mark R. Kimmich ,  Sudtida Lavangkul ,  Sopa Chevacharoenkul ,  Mark L. Jenson

IPC: H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22

CPC classification number: H01L27/0617 ,  G01R33/04 ,  G01R33/05

Abstract: An integrated circuit has a substrate, a circuit, a core structure, a first encapsulation layer, a second encapsulation layer, and an oxide layer. The circuit includes transistors with active regions developed on the substrate and a metal layer formed above the active regions to provide interconnections for the transistors. The core structure is formed above the metal layer. The first encapsulation layer covers the core structure, and it has a first thermal expansion coefficient. The second encapsulation layer covers the first encapsulation layer over the core structure, and it has a second thermal expansion coefficient that is different from the first thermal expansion coefficient. As a part of the stress relief structure, the oxide layer is formed above the second encapsulation layer. The oxide layer includes an oxide thickness sufficient to mitigate a thermal stress between the first and second encapsulation layers.

公开(公告)号：US11972942B2

公开(公告)日：2024-04-30

申请号：US17483286

申请日：2021-09-23

Applicant: Texas Instruments Incorporated

Inventor： Mona M. Eissa ,  Corinne Ann Gagnet ,  Christopher Scott Whitesell ,  Pushpa Mahalingam

IPC: H01L21/02

CPC classification number: H01L21/02236 ,  H01L21/02164 ,  H01L21/02255

Abstract: A method of forming an integrated circuit, including first, positioning a semiconductor wafer in a processing chamber; second, exposing portions of the semiconductor wafer, including introducing a first amount of hydrogen into the processing chamber and introducing a first amount of oxygen into the processing chamber; and, third, introducing at least one of a second amount of hydrogen or a second amount of oxygen into the processing chamber, the second amount of hydrogen greater than zero and less than the first amount of hydrogen and the second amount of oxygen greater than zero and less than the first amount of oxygen.

公开(公告)号：US11508721B2

公开(公告)日：2022-11-22

申请号：US17228631

申请日：2021-04-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mona M. Eissa ,  Mark R. Kimmich ,  Sudtida Lavangkul ,  Sopa Chevacharoenkul ,  Mark L. Jenson

IPC: H01L27/06 ,  G01R33/04 ,  G01R33/05

Abstract: An integrated circuit has a substrate, a circuit, a core structure, a first encapsulation layer, a second encapsulation layer, and an oxide layer. The circuit includes transistors with active regions developed on the substrate and a metal layer formed above the active regions to provide interconnections for the transistors. The core structure is formed above the metal layer. The first encapsulation layer covers the core structure, and it has a first thermal expansion coefficient. The second encapsulation layer covers the first encapsulation layer over the core structure, and it has a second thermal expansion coefficient that is different from the first thermal expansion coefficient. As a part of the stress relief structure, the oxide layer is formed above the second encapsulation layer. The oxide layer includes an oxide thickness sufficient to mitigate a thermal stress between the first and second encapsulation layers.

公开(公告)号：US11075157B2

公开(公告)日：2021-07-27

申请号：US16564849

申请日：2019-09-09

Applicant: Texas Instruments Incorporated

Inventor： Mona M. Eissa ,  Umamaheswari Aghoram ,  Pushpa Mahalingam ,  Erich Wesley Kinder ,  Bhaskar Srinivasan ,  Brian E. Goodlin

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/768

Abstract: An integrated circuit (IC) includes a semiconductor surface layer of a substrate including circuitry formed in the semiconductor surface layer configured together with a Metal-Insulator-Metal (MIM) capacitor. A multi-layer metal stack on the semiconductor surface layer includes a bottom plate contact metal layer including a bottom capacitor plate contact. A first interlevel dielectric (ILD) layer is over the bottom plate contact metal layer. The MIM capacitor includes a trench in the first ILD layer over the bottom capacitor plate contact, wherein the trench is lined by a bottom capacitor plate with a capacitor dielectric layer thereon, and a top capacitor plate on the capacitor dielectric layer. A fill material fills the trench to form a filled trench. A second ILD layer is over including the filled trench. A filled via through the second ILD layer provides a contact to a top plate contact on the top capacitor plate.

公开(公告)号：US10266950B2

公开(公告)日：2019-04-23

申请号：US15809143

申请日：2017-11-10

Applicant: Texas Instruments Incorporated

Inventor： Mona M. Eissa ,  Yousong Zhang ,  Mark Jenson

IPC: C23F1/28 ,  H01L21/02 ,  G01R33/04 ,  C09K13/06 ,  C23F1/02 ,  G03F7/00

Abstract: An etchant for simultaneously etching NiFe and AlN with approximately equal etch rates that comprises phosphoric acid, acetic acid, nitric acid and deionized water. Alternating layers of NiFe and AlN may be used to form a magnetic core of a fluxgate magnetometer in an integrated circuit. The wet etch provides a good etch rate of the alternating layers with good dimensional control and with a good resulting magnetic core profile. The alternating layers of NiFe and AlN may be encapsulated with a stress relief layer. A resist pattern may be used to define the magnetic core geometry. The overetch time of the wet etch may be controlled so that the magnetic core pattern extends at least 1.5 um beyond the base of the magnetic core post etch. The photo mask used to form the resist pattern may also be used to form a stress relief etch pattern.

公开(公告)号：US10718826B2

公开(公告)日：2020-07-21

申请号：US14557611

申请日：2014-12-02

Applicant: Texas Instruments Incorporated

Inventor： Mona M. Eissa ,  Dok Won Lee

IPC: G01R33/04 ,  G01R33/00

Abstract: An integrated circuit includes a fluxgate magnetometer. The magnetic core of the fluxgate magnetometer is encapsulated with a layer of encapsulant of a nonmagnetic metal or a nonmagnetic alloy. The layer of encapsulate provides stress relaxation between the magnetic core material and the surrounding dielectric. A method for forming an integrated circuit has the magnetic core of a fluxgate magnetometer encapsulated with a layer of a nonmagnetic metal or nonmagnetic alloy to eliminate delamination and to substantially reduce cracking of the dielectric that surrounds the magnetic core.

公开(公告)号：US09840781B2

公开(公告)日：2017-12-12

申请号：US14557546

申请日：2014-12-02

Applicant: Texas Instruments Incorporated

Inventor： Mona M. Eissa ,  Yousong Zhang ,  Mark Jenson

IPC: C23F1/28 ,  H01L21/02 ,  G01R33/04 ,  C09K13/06 ,  C23F1/02 ,  G03F7/00

CPC classification number: C23F1/28 ,  C09K13/06 ,  C23F1/02 ,  G01R33/04 ,  G03F7/0005 ,  H01L21/02107

Abstract: An etchant for simultaneously etching NiFe and AlN with approximately equal etch rates that comprises phosphoric acid, acetic acid, nitric acid and deionized water. Alternating layers of NiFe and AlN may be used to form a magnetic core of a fluxgate magnetometer in an integrated circuit. The wet etch provides a good etch rate of the alternating layers with good dimensional control and with a good resulting magnetic core profile. The alternating layers of NiFe and AlN may be encapsulated with a stress relief layer. A resist pattern may be used to define the magnetic core geometry. The overetch time of the wet etch may be controlled so that the magnetic core pattern extends at least 1.5 um beyond the base of the magnetic core post etch. The photo mask used to form the resist pattern may also be used to form a stress relief etch pattern.