公开(公告)号：US11755322B2

公开(公告)日：2023-09-12

申请号：US16580490

申请日：2019-09-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Duc Quang Bui ,  Peter Richard Dent

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30032 ,  G06F9/30043

Abstract: Disclosed embodiments relate to methods of using a processor to load and duplicate scalar data from a source into a destination register. The data may be duplicated in byte, half word, word or double word parts, according to a duplication pattern.

公开(公告)号：US20230418605A1

公开(公告)日：2023-12-28

申请号：US18243326

申请日：2023-09-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Duc Quang Bui ,  Peter Richard Dent

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30032 ,  G06F9/30043

Abstract: Disclosed embodiments relate to methods of using a processor to load and duplicate scalar data from a source into a destination register. The data may be duplicated in byte, half word, word or double word parts, according to a duplication pattern.

公开(公告)号：US11294826B2

公开(公告)日：2022-04-05

申请号：US16551587

申请日：2019-08-26

Applicant: Texas Instruments Incorporated

Inventor： Timothy David Anderson ,  Mujibur Rahman ,  Dheera Balasubramanian Samudrala ,  Peter Richard Dent ,  Duc Quang Bui

IPC: G06F9/315 ,  G06F12/0875 ,  G06F11/00 ,  G06F15/76 ,  G06F12/1045 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F11/10 ,  G06F9/32 ,  G06F12/0897 ,  G06F12/0862 ,  G06F12/1009 ,  G06F15/78

Abstract: A method is provided that includes performing, by a processor in response to a vector permutation instruction, permutation of values stored in lanes of a vector to generate a permuted vector, wherein the permutation is responsive to a control storage location storing permute control input for each lane of the permuted vector, wherein the permute control input corresponding to each lane of the permuted vector indicates a value to be stored in the lane of the permuted vector, wherein the permute control input for at least one lane of the permuted vector indicates a value of a selected lane of the vector is to be stored in the at least one lane, and storing the permuted vector in a storage location indicated by an operand of the vector permutation instruction.

公开(公告)号：US20210349832A1

公开(公告)日：2021-11-11

申请号：US17384858

申请日：2021-07-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Mujibur Rahman ,  Dheera Balasubramanian Samudrala ,  Peter Richard Dent ,  Duc Quang Bui

IPC: G06F12/1045 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F11/00 ,  G06F11/10 ,  G06F9/32 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/0862 ,  G06F12/1009

Abstract: A method is provided that includes performing, by a processor in response to a vector permutation instruction, permutation of values stored in lanes of a vector to generate a permuted vector, wherein the permutation is responsive to a control storage location storing permute control input for each lane of the permuted vector, wherein the permute control input corresponding to each lane of the permuted vector indicates a value to be stored in the lane of the permuted vector, wherein the permute control input for at least one lane of the permuted vector indicates a value of a selected lane of the vector is to be stored in the at least one lane, and storing the permuted vector in a storage location indicated by an operand of the vector permutation instruction.

公开(公告)号：US20200089495A1

公开(公告)日：2020-03-19

申请号：US16580490

申请日：2019-09-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Duc Quang Bui ,  Peter Richard Dent

IPC: G06F9/30

Abstract: Disclosed embodiments relate to methods of using a processor to load and duplicate scalar data from a source into a destination register. The data may be duplicated in byte, half word, word or double word parts, according to a duplication pattern.

公开(公告)号：US09489197B2

公开(公告)日：2016-11-08

申请号：US14327022

申请日：2014-07-09

Applicant: Texas Instruments Incorporated

Inventor： Mujibur Rahman ,  Peter Richard Dent ,  Timothy David Anderson ,  Duc Quang Bui

IPC: G06F17/15 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3001 ,  G06F9/30036 ,  G06F9/30094 ,  G06F9/3013 ,  G06F9/3853 ,  G06F9/3895 ,  G06F17/15

Abstract: This invention is a digital signal processor capable of performing correlation of data with pseudo noise for code division multiple access (CDMA) decoding using clusters. Each cluster includes plural multipliers. The multipliers multiply real and imaginary parts of packed data by corresponding pseudo noise data. Within a cluster the real parts and the imaginary parts of the products are summed separately. This forms plural complex number outputs equal in number to the number of clusters. The pseudo noise data is offset relative to the data input differing amounts for different clusters. The clusters are divided into first half clusters receiving data from even numbered slots and second half clusters receiving data from odd numbered slots. The correlation unit includes a mask input to selectively zero a multiplier product.

Abstract translation: 本发明是一种数字信号处理器，能够执行数据与伪噪声的相关，以便使用簇进行码分多址（CDMA）解码。 每个簇包括多个乘法器。 乘法器将打包数据的实部和虚部乘以相应的伪噪声数据。 在集群中，产品的实部和虚部分别相加。 这形成数量与簇数相等的多个复数输出。 伪噪声数据相对于数据输入偏移不同的簇的不同量。 这些簇被分成从偶数编号的时隙接收数据的第一个半组和从奇数编号的时隙接收数据的第二个半组。 相关单元包括用于选择性地使乘法器乘积为零的掩码输入。

公开(公告)号：US20150019842A1

公开(公告)日：2015-01-15

申请号：US14327022

申请日：2014-07-09

Applicant: Texas Instruments Incorporated

Inventor： Mujibur Rahman ,  Peter Richard Dent ,  Timothy David Anderson ,  Duc Quang Bui

IPC: G06F9/30

CPC classification number: G06F9/3001 ,  G06F9/30036 ,  G06F9/30094 ,  G06F9/3013 ,  G06F9/3853 ,  G06F9/3895 ,  G06F17/15

Abstract: This invention is a digital signal processor capable of performing correlation of data with pseudo noise for code division multiple access (CDMA) decoding using clusters. Each cluster includes plural multipliers. The multipliers multiply real and imaginary parts of packed data by corresponding pseudo noise data. Within a cluster the real parts and the imaginary parts of the products are summed separately. This forms plural complex number outputs equal in number to the number of clusters. The pseudo noise data is offset relative to the data input differing amounts for different clusters. The clusters are divided into first half clusters receiving data from even numbered slots and second half clusters receiving data from odd numbered slots. The correlation unit includes a mask input to selectively zero a multiplier product.

Abstract translation: 本发明是一种数字信号处理器，能够执行数据与伪噪声的相关，以便使用簇进行码分多址（CDMA）解码。 每个簇包括多个乘法器。 乘法器将打包数据的实部和虚部乘以相应的伪噪声数据。 在集群中，产品的实部和虚部分别相加。 这形成数量与簇数相等的多个复数输出。 伪噪声数据相对于数据输入偏移不同的簇的不同量。 这些簇被分成从偶数编号的时隙接收数据的第一个半组和从奇数编号的时隙接收数据的第二个半组。 相关单元包括用于选择性地使乘法器乘积为零的掩码输入。

公开(公告)号：US11614940B2

公开(公告)日：2023-03-28

申请号：US17215013

申请日：2021-03-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Duc Bui ,  Peter Richard Dent ,  Timothy D. Anderson

IPC: G06F9/30

Abstract: A method to compare first and second source data in a processor in response to a vector maximum with indexing instruction includes specifying first and second source registers containing first and second source data, a destination register storing compared data, and a predicate register. Each of the registers includes a plurality of lanes. The method includes executing the instruction by, for each lane in the first and second source register, comparing a value in the lane of the first source register to a value in the corresponding lane of the second source register to identify a maximum value, storing the maximum value in a corresponding lane of the destination register, asserting a corresponding lane of the predicate register if the maximum value is from the first source register, and de-asserting the corresponding lane of the predicate register if the maximum value is from the second source register.

公开(公告)号：US11074193B2

公开(公告)日：2021-07-27

申请号：US16551587

申请日：2019-08-26

Applicant: Texas Instruments Incorporated

Inventor： Timothy David Anderson ,  Mujibur Rahman ,  Dheera Balasubramanian Samudrala ,  Peter Richard Dent ,  Duc Quang Bui

IPC: G06F9/315 ,  G06F12/0875 ,  G06F11/00 ,  G06F15/76 ,  G06F12/1045 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F11/10 ,  G06F9/32 ,  G06F12/0897 ,  G06F12/0862 ,  G06F12/1009 ,  G06F15/78

Abstract: A method is provided that includes performing, by a processor in response to a vector permutation instruction, permutation of values stored in lanes of a vector to generate a permuted vector, wherein the permutation is responsive to a control storage location storing permute control input for each lane of the permuted vector, wherein the permute control input corresponding to each lane of the permuted vector indicates a value to be stored in the lane of the permuted vector, wherein the permute control input for at least one lane of the permuted vector indicates a value of a selected lane of the vector is to be stored in the at least one lane, and storing the permuted vector in a storage location indicated by an operand of the vector permutation instruction.

公开(公告)号：US10963252B2

公开(公告)日：2021-03-30

申请号：US16422501

申请日：2019-05-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Duc Bui ,  Peter Richard Dent ,  Timothy D. Anderson

IPC: G06F9/30

Abstract: A method to compare first and second source data in a processor in response to a vector maximum with indexing instruction includes specifying first and second source registers containing first and second source data, a destination register storing compared data, and a predicate register. Each of the registers includes a plurality of lanes. The method includes executing the instruction by, for each lane in the first and second source register, comparing a value in the lane of the first source register to a value in the corresponding lane of the second source register to identify a maximum value, storing the maximum value in a corresponding lane of the destination register, asserting a corresponding lane of the predicate register if the maximum value is from the first source register, and de-asserting the corresponding lane of the predicate register if the maximum value is from the second source register.