公开(公告)号：US20230336887A1

公开(公告)日：2023-10-19

申请号：US18343018

申请日：2023-06-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Gang HUA ,  Rajasekhar Reddy ALLU ,  Mihir Narendra MODY ,  Niraj NANDAN ,  Mayank MANGLA ,  Pandy KALIMUTHU

IPC: H04N25/611 ,  G06T3/40 ,  G06T1/60 ,  H04N25/13

CPC classification number: H04N25/611 ,  G06T3/4015 ,  G06T1/60 ,  H04N25/13

Abstract: In an advanced driver-assistance system (ADAS), RAW sensor image processing for a machine vision (MV) application is important. Due to different color, e.g., red/green/blue (RGB), color components, being focused by the lens at different locations in image plane, the lateral chromatic aberration phenomenon may sometimes be observed, which causes false color around edges in the final image output, especially for high contrast edges, which can impede MV applications. Disclosed herein are low-latency, efficient, optimized designs for chromatic aberration correction (CAC) components. An in-pipeline CAC design may be used to perform on-the-fly CAC without any out-of-pipeline memory traffic; enable use of wide dynamic range (WDR) sensors; uses bicubic interpolation; support vertical and horizontal chromatic aberration color channel offsets, reduce CAC line memory requirements, and support flexible look-up table (LUT) down-sampling factors to improve the spatial precision of correction and accommodate popular image sensor resolutions.

公开(公告)号：US20200210351A1

公开(公告)日：2020-07-02

申请号：US16234508

申请日：2018-12-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir MODY ,  Niraj NANDAN ,  Hetul SANGHVI ,  Brian CHAE ,  Rajasekhar Reddy ALLU ,  Jason A.T. JONES ,  Anthony LELL ,  Anish REGHUNATH

IPC: G06F13/16 ,  G06F13/28 ,  H04N5/765 ,  G06T1/20

Abstract: A processing accelerator includes a shared memory, and a stream accelerator, a memory-to-memory accelerator, and a common DMA controller coupled to the shared memory. The stream accelerator is configured to process a real-time data stream, and to store stream accelerator output data generated by processing the real-time data stream in the shared memory. The memory-to-memory accelerator is configured to retrieve input data from the shared memory, to process the input data, and to store, in the shared memory, memory-to-memory accelerator output data generated by processing the input data. The common DMA controller is configured to retrieve stream accelerator output data from the shared memory and transfer the stream accelerator output data to memory external to the processing accelerator; and to retrieve the memory-to-memory accelerator output data from the shared memory and transfer the memory-to-memory accelerator output data to memory external to the processing accelerator.

公开(公告)号：US20240214511A1

公开(公告)日：2024-06-27

申请号：US18599324

申请日：2024-03-08

Applicant: Texas Instruments Incorporated

Inventor： Mihir Narendra MODY ,  Brijesh JADAV ,  Gang HUA ,  Niraj NANDAN ,  Rajasekhar Reddy ALLU ,  Ankur ANKUR ,  Mayank MANGLA

IPC: H04N5/262 ,  G06T3/40 ,  G06T7/12 ,  G06T7/60 ,  G06T11/00

CPC classification number: H04N5/2628 ,  G06T3/40 ,  G06T7/12 ,  G06T7/60 ,  G06T11/00

Abstract: A technique for determining regions and block sizes for configuring a perspective transformation engine including determining a set of scale ratios for images captured by a camera, generating a scale ratio image based on the set of scale ratios, determining a set of boundary ranges for the scale ratio image, generating a binary scale ratio image using the set of scale ratios of the scale ratio image, determining a set of regions based on the set of boundary ranges for the binary scale ratio image, determining a block size for each region of the determined set of regions, and outputting the determined set of regions and the determined block sizes.

公开(公告)号：US20230169689A1

公开(公告)日：2023-06-01

申请号：US17538268

申请日：2021-11-30

Applicant: Texas Instruments Incorporated

Inventor： Gang HUA ,  Mihir Narendra MODY ,  Niraj NANDAN ,  Shashank DABRAL ,  Rajasekhar Reddy ALLU ,  Denis Roland BEAUDOIN

IPC: G06T7/90 ,  G06T1/20

CPC classification number: G06T7/90 ,  G06T1/20 ,  G06T2207/20208 ,  G06T2207/10024

Abstract: Techniques for image processing including receiving input image data, wherein the input image data includes data associated with a clear color channel, receiving a color offset value associated with a color channel, wherein color values for the color channel are not provided in the input image data, based on the color offset value, generating intermediate estimated color values for the color channel, wherein generating the intermediate estimated color values includes: clipping color values that have a magnitude greater than the color offset value, and adjusting color values that have a magnitude less than the color offset value based on the color offset value, applying a color correction function to the intermediate estimated color values based on the color offset value to determine color corrected estimated color values, and outputting the color corrected estimated color values.

公开(公告)号：US20250080868A1

公开(公告)日：2025-03-06

申请号：US18954910

申请日：2024-11-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Gang HUA ,  Rajasekhar Reddy ALLU ,  Mihir Narendra MODY ,  Niraj NANDAN ,  Mayank MANGLA ,  Pandy KALIMUTHU

IPC: H04N25/611 ,  G06T1/60 ,  G06T3/4015 ,  H04N25/13

Abstract: In an advanced driver-assistance system (ADAS), RAW sensor image processing for a machine vision (MV) application is important. Due to different color, e.g., red/green/blue (RGB), color components, being focused by the lens at different locations in image plane, the lateral chromatic aberration phenomenon may sometimes be observed, which causes false color around edges in the final image output, especially for high contrast edges, which can impede MV applications. Disclosed herein are low-latency, efficient, optimized designs for chromatic aberration correction (CAC) components. An in-pipeline CAC design may be used to perform on-the-fly CAC without any out-of-pipeline memory traffic; enable use of wide dynamic range (WDR) sensors; uses bicubic interpolation; support vertical and horizontal chromatic aberration color channel offsets, reduce CAC line memory requirements, and support flexible look-up table (LUT) down-sampling factors to improve the spatial precision of correction and accommodate popular image sensor resolutions.

公开(公告)号：US20240428369A1

公开(公告)日：2024-12-26

申请号：US18828069

申请日：2024-09-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Niraj NANDAN ,  Rajasekhar Reddy ALLU ,  Mihir Narendra MODY

IPC: G06T1/60 ,  G06F9/50 ,  G06F9/54

Abstract: A lens distortion correction function operates by backmapping output images to the uncorrected, distorted input images. As a vision image processor completes processing on the image data lines needed for the lens distortion correction function to operate on a group of output, undistorted image lines, the lens distortion correction function begins processing the image data. This improves image processing pipeline delays by overlapping the operations. The vision image processor provides output image data to a circular buffer in SRAM, rather than providing it to DRAM. The lens distortion correction function operates from the image data in the circular buffer. By operating from the SRAM circular buffer, access to the DRAM for the highly fragmented backmapping image data read operations is removed, improving available DRAM bandwidth. By using a circular buffer, less space is needed in the SRAM. The improved memory operations further improve the image processing pipeline delays.

公开(公告)号：US20220114120A1

公开(公告)日：2022-04-14

申请号：US17558252

申请日：2021-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir MODY ,  Niraj NANDAN ,  Hetul SANGHVI ,  Brian CHAE ,  Rajasekhar Reddy ALLU ,  Jason A.T. JONES ,  Anthony LELL ,  Anish REGHUNATH

IPC: G06F13/16 ,  G06T1/20 ,  H04N5/765 ,  G06F13/28

Abstract: A processing accelerator includes a shared memory, and a stream accelerator, a memory-to-memory accelerator, and a common DMA controller coupled to the shared memory. The stream accelerator is configured to process a real-time data stream, and to store stream accelerator output data generated by processing the real-time data stream in the shared memory. The memory-to-memory accelerator is configured to retrieve input data from the shared memory, to process the input data, and to store, in the shared memory, memory-to-memory accelerator output data generated by processing the input data. The common DMA controller is configured to retrieve stream accelerator output data from the shared memory and transfer the stream accelerator output data to memory external to the processing accelerator; and to retrieve the memory-to-memory accelerator output data from the shared memory and transfer the memory-to-memory accelerator output data to memory external to the processing accelerator.

公开(公告)号：US20210209722A1

公开(公告)日：2021-07-08

申请号：US16909710

申请日：2020-06-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Niraj NANDAN ,  Rajasekhar Reddy ALLU ,  Mihir Narendra MODY

IPC: G06T1/60 ,  G06F9/50 ,  G06F9/54

Abstract: A lens distortion correction function operates by backmapping output images to the uncorrected, distorted input images. As a vision image processor completes processing on the image data lines needed for the lens distortion correction function to operate on a group of output, undistorted image lines, the lens distortion correction function begins processing the image data. This improves image processing pipeline delays by overlapping the operations. The vision image processor provides output image data to a circular buffer in SRAM, rather than providing it to DRAM. The lens distortion correction function operates from the image data in the circular buffer. By operating from the SRAM circular buffer, access to the DRAM for the highly fragmented backmapping image data read operations is removed, improving available DRAM bandwidth. By using a circular buffer, less space is needed in the SRAM. The improved memory operations further improve the image processing pipeline delays.

公开(公告)号：US20230117485A1

公开(公告)日：2023-04-20

申请号：US18084635

申请日：2022-12-20

Applicant: Texas Instruments Incorporated

Inventor： Mihir Narendra MODY ,  Niraj NANDAN ,  Rajasekhar Reddy ALLU

IPC: G06F3/06 ,  G06F13/28

Abstract: An integrated circuit includes: a local memory; and a first processing circuit coupled to the local memory. The first processing component is configured to: receive a first set of image data; perform a first image processing operation on the first set of image data to produce a second set of image data; and store at least some of the second set of image data into the local memory. The integrated circuit also includes a second processing circuit coupled to the local memory and configured to: receive at least some of the second set of image data from the local memory; and perform a second image processing operation on the second set of image data to produce a third set of image data.

公开(公告)号：US20220263979A1

公开(公告)日：2022-08-18

申请号：US17739291

申请日：2022-05-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Gang HUA ,  Mihir Narendra MODY ,  Rajasekhar Reddy ALLU ,  Niraj NANDAN ,  Shashank DABRAL

IPC: H04N5/217 ,  H04N9/04 ,  H04N5/357

Abstract: In some examples, a method comprises receiving pixel data from an image capture device having a color filter, wherein the pixel data represents a portion of an image. The method further includes performing wavelet decomposition on the pixel data to produce decomposed pixel data and determining a local intensity of the pixel data. The method also includes determining a noise threshold value based on the local intensity and a noise intensity function that is based on the color filter; determining a noise value for the pixel data based on the decomposed pixel data and the noise threshold value; and correcting the pixel data based on the noise value to produce an output image.