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公开(公告)号：US20250023558A1
公开(公告)日：2025-01-16
申请号：US18428966
申请日：2024-01-31
Applicant: Texas Instruments Incorporated
Inventor： Win N Maung , Richard Edwin Hubbard , Jonathan Lee Valdez , Mark Edward Wentroble , Justin Silver , Anirudh Rustagi , Ashwin Ramachandran
Abstract: An example apparatus includes: a capacitor having a terminal; comparator circuitry having an input terminal and an output terminal, the input terminal of the comparator circuitry coupled to the terminal of the capacitor; timer circuitry having an input terminal and an output terminal, the input terminal of the timer circuitry coupled to the output terminal of the comparator circuitry; and configuration determination circuitry having an input and an output, the input of the configuration determination circuitry coupled to the output of the timer circuitry; and a configuration register having an input coupled to the output of the configuration determination circuitry.
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公开(公告)号：US10560282B2
公开(公告)日：2020-02-11
申请号：US15854583
申请日：2017-12-26
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Abhijeeth Aarey Premanath , Richard Edwin Hubbard , Maxwell Guy Robertson , Lokesh Kumar Gupta , Mark Edward Wentroble , Roland Sperlich , Dejan Radic
Abstract: Two CAN bus transceivers utilized in a single integrated circuit package with the CAN bus connections between the two transceivers being inverted. Thus, one transceiver is connected to the CAN bus high and low lines while the other transceiver is connected to the CAN bus low and high lines. Both transceivers power up in a standby condition and each transceiver is monitoring for wake up signals on the CAN bus. The transceiver that is correctly connected to the CAN bus detects wake up signals. When the wake up signals are detected at that transceiver, that transceiver is brought to full operating state and the other transceiver is placed in a full standby condition. Additional input resistance is provided with each transceiver to maintain the proper input resistance for the integrated circuit.
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公开(公告)号：US20180351765A1
公开(公告)日：2018-12-06
申请号：US15854583
申请日：2017-12-26
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Abhijeeth Aarey Premanath , Richard Edwin Hubbard , Maxwell Guy Robertson , Lokesh Kumar Gupta , Mark Edward Wentroble , Roland Sperlich , Dejan Radic
CPC classification number: H04L12/40032 , H04L12/12 , H04L12/40039 , H04L2012/40215 , H04L2012/40273
Abstract: Two CAN bus transceivers utilized in a single integrated circuit package with the CAN bus connections between the two transceivers being inverted. Thus, one transceiver is connected to the CAN bus high and low lines while the other transceiver is connected to the CAN bus low and high lines. Both transceivers power up in a standby condition and each transceiver is monitoring for wake up signals on the CAN bus. The transceiver that is correctly connected to the CAN bus detects wake up signals. When the wake up signals are detected at that transceiver, that transceiver is brought to full operating state and the other transceiver is placed in a full standby condition. Additional input resistance is provided with each transceiver to maintain the proper input resistance for the integrated circuit.
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公开(公告)号：US09940298B2
公开(公告)日：2018-04-10
申请号：US14659582
申请日：2015-03-16
Applicant: Texas Instruments Incorporated
CPC classification number: G06F13/4286 , G06F13/4081 , Y02D10/14 , Y02D10/151
Abstract: In a segmented data path, a source is able to “discover” whether any tunable repeater nodes are present. When one or more tunable repeaters are discovered, the source may adjust its link initialization sequence accordingly to train each “hop” individually and thereafter individually configure each intermediary repeater.
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公开(公告)号：US11677370B2
公开(公告)日：2023-06-13
申请号：US17487241
申请日：2021-09-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
CPC classification number: H03F3/45192 , H04L12/40 , H03F2200/78 , H03F2203/30061 , H03F2203/45508 , H04L2012/40215
Abstract: A circuit (e.g., implemented as part of a controller area network (CAN) bus receiver includes a pre-amplifier stage having first and second outputs. The circuit also includes a comparator having first and second inputs. The first input is coupled to the first output of the pre-amplifier stage, and the second input is coupled to the second output of the pre-amplifier stage. The comparator includes an input differential transistor pair, a second pair of transistors coupled to the input differential transistor pair in a cascode configuration, and a push-pull output stage coupled to the second pair of transistors.
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Patent Agency Ranking
公开(公告)号：US11159135B2
公开(公告)日：2021-10-26
申请号：US16862089
申请日：2020-04-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Abstract: A circuit (e.g., implemented as part of a controller area network (CAN) bus receiver includes a pre-amplifier stage having first and second outputs. The circuit also includes a comparator having first and second inputs. The first input is coupled to the first output of the pre-amplifier stage, and the second input is coupled to the second output of the pre-amplifier stage. The comparator includes an input differential transistor pair, a second pair of transistors coupled to the input differential transistor pair in a cascode configuration, and a push-pull output stage coupled to the second pair of transistors.
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公开(公告)号：US10884069B2
公开(公告)日：2021-01-05
申请号：US16101213
申请日：2018-08-10
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Richard Edwin Hubbard , Abhijeeth Aarey Premanath , Terry Mayhugh , Mark Edward Wentroble , Wesley Ryan Ray
Abstract: A CAN bus transceiver includes CAN bus fault detection circuitry that can provide detailed information to simplify the task of the service technician when there is a CAN bus fault. Voltage and current measurements of the CAN bus are made and from them a fault type is determined. A time-domain reflectometer monitors the CAN bus signals for transmitted and reflected signals and from them a distance to the fault is determined. Either or both values are provided to a service technician to allow error determination and correction.
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公开(公告)号：US11176067B2
公开(公告)日：2021-11-16
申请号：US16909396
申请日：2020-06-23
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Richard Edwin Hubbard , Richard Sterling Broughton , Vijayalakshmi Devarajan , Mark Edward Wentroble
Abstract: An integrated circuit includes a combined serial data output and interrupt output terminal, a serial communication control circuit; an interrupt generation circuit, and an output circuit. The output circuit includes a serial data input, an interrupt input, and a combined serial data and interrupt output. The serial data input is coupled to a serial data output of the serial communication circuit. The interrupt input is coupled to an interrupt output of the interrupt generation circuit. The combined serial data and interrupt output is coupled to the combined serial data output and interrupt output terminal.
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公开(公告)号：US11175685B2
公开(公告)日：2021-11-16
申请号：US16914938
申请日：2020-06-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
IPC: G05F1/46 , H03K17/00 , H03K5/24 , H03K3/3565
Abstract: An integrated circuit includes an input terminal, an input buffer circuit, an interface voltage control circuit, an output voltage selection circuit, an output driver circuit, and an output terminal. The input buffer circuit is coupled to the input terminal. The interface voltage control circuit is coupled to the input terminal. The output voltage selection circuit is coupled to the interface voltage control circuit. The output driver circuit is coupled to the output voltage selection circuit. The output terminal is coupled to the output driver circuit.
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公开(公告)号：US20210325951A1
公开(公告)日：2021-10-21
申请号：US17178789
申请日：2021-02-18
Applicant: Texas Instruments Incorporated
Inventor： Vijayalakshmi DEVARAJAN , Wesley Ryan RAY , Richard Edwin Hubbard
IPC: G06F1/3234 , G06F1/26 , G06F13/42
Abstract: A system basis chip (SBC) includes a serial peripheral interface for communication with a processor, a set of registers for storing information operable to control an external communication interface device, and a control signal output adapted to be coupled to the external communication interface device. In some implementations, the set of registers includes a first register for information indicative of a function of the control signal, and a second register for information indicative of a value of the control signal. The function of the control signal for the external communication interface device can be a supply voltage interrupt, a watchdog interrupt event, a counter-based watchdog interrupt event, a local wakeup request, a bus wakeup request, an entrance into a fail-safe mode of operation, or a general purpose output signal. In some implementations, the SBC also includes a supply voltage output adapted to be coupled to the external communication interface device.
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