公开(公告)号：US20140136138A1

公开(公告)日：2014-05-15

申请号：US13674941

申请日：2012-11-12

Applicant: TEXAS INSTRUMENTS, INCORPORATED

Inventor： Joonsung Park ,  Srinadh Madhavapeddi ,  Christopher Barr

IPC: G01R31/28 ,  G06F17/00

CPC classification number: G06F17/00 ,  G01N29/46 ,  G01R23/16 ,  G01R31/28 ,  G01R31/3172 ,  G01R31/31721 ,  G01R31/31727 ,  G06F11/2294 ,  G06F11/24 ,  G06F17/141

Abstract: A computing device uses a recursive discrete Fourier transform (RDFT) engine to reduce time required by a frequency transform module, memory required to hold intermediate products, and/or computing resources used for the testing. In an embodiment the windowing function is integrated and processed simultaneously with the recursive DFT funcions. A frequency-bin power module is configured to determine the frequency bin within the set of frequency bins that has a greatest signal power at various levels of recursion.

Abstract translation: 计算设备使用递归离散傅里叶变换（RDFT）引擎来减少频率变换模块所需的时间，保存中间产品所需的存储器和/或用于测试的计算资源。 在一个实施例中，窗口功能与递归DFT功能同时整合和处理。 频率仓功率模块被配置为确定在各种递归水平下具有最大信号功率的频率组集合内的频率仓。

公开(公告)号：US10536258B2

公开(公告)日：2020-01-14

申请号：US15996444

申请日：2018-06-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hunsoo Choo ,  Hamid Safiri ,  Nikolaus Klemmer ,  Jaimin Mehta ,  Srinadh Madhavapeddi ,  Charles Kasimer Sestok ,  Vijayavardhan Baireddy

IPC: H04L7/00 ,  G06F1/10

Abstract: Multi-domain clock generation with skew compensation is based on free-running counters in each of the multiple clock domains. Multi-domain clock generation circuitry provides at least first and second domain clocks generated with randomization, each based on an input clock with an input clock frequency, the domain clocks having a relative clock skew that is varied over time in magnitude and direction. A first circuit in a first clock domain, configured for operation with the first domain clock, includes a first free-running counter with a pre-defined first selected roll-over count, to generate a first free-running count (N1(k)) based on the first domain clock. A second circuit in a second clock domain is configured for operation with the second domain clock, and includes a second free-running counter with a pre-defined second selected roll-over count, to generate a second free-running count (N2(k)) based on the second domain clock.

公开(公告)号：US20190372747A1

公开(公告)日：2019-12-05

申请号：US15996444

申请日：2018-06-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hunsoo Choo ,  Hamid Safiri ,  Nikolaus Klemmer ,  Jaimin Mehta ,  Srinadh Madhavapeddi ,  Charles Kasimer Sestok ,  Vijayavardhan Baireddy

IPC: H04L7/00 ,  G06F1/10

Abstract: Multi-domain clock generation with skew compensation is based on free-running counters in each of the multiple clock domains. Multi-domain clock generation circuitry provides at least first and second domain clocks generated with randomization, each based on an input clock with an input clock frequency, the domain clocks having a relative clock skew that is varied over time in magnitude and direction. A first circuit in a first clock domain, configured for operation with the first domain clock, includes a first free-running counter with a pre-defined first selected roll-over count, to generate a first free-running count (N1(k)) based on the first domain clock. A second circuit in a second clock domain is configured for operation with the second domain clock, and includes a second free-running counter with a pre-defined second selected roll-over count, to generate a second free-running count (N2(k)) based on the second domain clock.

公开(公告)号：US09342482B2

公开(公告)日：2016-05-17

申请号：US13674941

申请日：2012-11-12

Applicant: Texas Instruments, Incorporated.

Inventor： Joonsung Park ,  Srinadh Madhavapeddi ,  Christopher Barr

IPC: G01R23/00 ,  G06F17/00 ,  G01R23/16 ,  G01R31/28 ,  G01R31/317 ,  G06F11/22 ,  G06F11/24 ,  G01N29/46 ,  G06F17/14

CPC classification number: G06F17/00 ,  G01N29/46 ,  G01R23/16 ,  G01R31/28 ,  G01R31/3172 ,  G01R31/31721 ,  G01R31/31727 ,  G06F11/2294 ,  G06F11/24 ,  G06F17/141

Abstract: A computing device uses a recursive discrete Fourier transform (RDFT) engine to reduce time required by a frequency transform module, memory required to hold intermediate products, and/or computing resources used for the testing. In an embodiment the windowing function is integrated and processed simultaneously with the recursive DFT funcions. A frequency-bin power module is configured to determine the frequency bin within the set of frequency bins that has a greatest signal power at various levels of recursion.

Abstract translation: 计算设备使用递归离散傅里叶变换（RDFT）引擎来减少频率变换模块所需的时间，保存中间产品所需的存储器和/或用于测试的计算资源。 在一个实施例中，窗口功能与递归DFT功能同时整合和处理。 频率仓功率模块被配置为确定在各种递归水平下具有最大信号功率的频率组集合内的频率仓。

公开(公告)号：US11341015B2

公开(公告)日：2022-05-24

申请号：US16588449

申请日：2019-09-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy Murphy ,  Srinadh Madhavapeddi ,  Terry Lee Sculley

IPC: G06F11/00 ,  G06F11/30 ,  G06F11/22 ,  G06F11/07 ,  G06F11/20

Abstract: A system includes a battery and a monitoring circuit coupled to the battery. The monitoring circuit includes a sense circuit and a peripheral device coupled to the sense circuit. The peripheral device includes a universal asynchronous receiver-transmitter (UART) receiver having an adaptive sample timing circuit with a numerically-controlled oscillator (NCO) circuit. The peripheral device also includes memory coupled to the UART receiver and configured to store battery monitoring data.

公开(公告)号：US10218338B1

公开(公告)日：2019-02-26

申请号：US15782200

申请日：2017-10-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nikolaus Klemmer ,  Chan Fernando ,  Jaimin Mehta ,  Srinadh Madhavapeddi ,  Hamid Safiri ,  Atul Kumar Jain

IPC: H03K3/84 ,  H03K5/1252 ,  H03K17/16

Abstract: Aperiodic clock generation with clock spur suppression is based on cascaded randomizers, such as for mixed signal devices. A clock generator circuit includes an input node to receive the input periodic clock signal having an input-clock frequency. A first randomizer circuit coupled to receive the input clock signal from the input node, to perform signal randomization to suppress spurious signal content associated with (a) the input clock signal, and (b) the first randomizer circuit, and to generate an intermediate clock signal. A second concatenated randomizer circuit is coupled to receive the intermediate clock signal, to perform signal randomization to suppress spurious signal content associated with (a) the intermediated clock signal, and (b) the second randomizer circuit, and to generate an aperiodic output clock signal having a pre-defined average output-clock frequency that is less than the input-clock frequency. Example randomizers are a delta-sigma divider and a pulse swallower (in any order).