公开(公告)号：US11799014B2

公开(公告)日：2023-10-24

申请号：US17576727

申请日：2022-01-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Anhao Cheng ,  Fang-Ting Kuo

IPC: H01L29/80 ,  H01L31/112 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L49/02 ,  H03K19/0185

CPC classification number: H01L29/66484 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823857 ,  H01L27/0922 ,  H01L28/40 ,  H01L29/66492 ,  H03K19/018521 ,  H01L21/823878

Abstract: A method and structure providing a high-voltage transistor (HVT) including a gate dielectric, where at least part of the gate dielectric is provided within a trench disposed within a substrate. In some aspects, a gate oxide thickness may be controlled by way of a trench depth. By providing the HVT with a gate dielectric formed within a trench, embodiments of the present disclosure provide for the top gate stack surface of the HVT and the top gate stack surface of a low-voltage transistor (LVT), formed on the same substrate, to be substantially co-planar with each other, while providing a thick gate oxide for the HVTs. Further, because the top gate stack surface of HVT and the top gate stack surface of the LVT are substantially co-planar with each other, over polishing of the HVT gate stack can be avoided.

公开(公告)号：US20200027964A1

公开(公告)日：2020-01-23

申请号：US16587003

申请日：2019-09-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Anhao Cheng ,  Fang-Ting Kuo

IPC: H01L29/66 ,  H01L21/8234 ,  H03K19/0185 ,  H01L27/092 ,  H01L49/02 ,  H01L21/8238

Abstract: A method and structure providing a high-voltage transistor (HVT) including a gate dielectric, where at least part of the gate dielectric is provided within a trench disposed within a substrate. In some aspects, a gate oxide thickness may be controlled by way of a trench depth. By providing the HVT with a gate dielectric formed within a trench, embodiments of the present disclosure provide for the top gate stack surface of the HVT and the top gate stack surface of a low-voltage transistor (LVT), formed on the same substrate, to be substantially co-planar with each other, while providing a thick gate oxide for the HVTs. Further, because the top gate stack surface of HVT and the top gate stack surface of the LVT are substantially co-planar with each other, over polishing of the HVT gate stack can be avoided.

公开(公告)号：US12218181B2

公开(公告)日：2025-02-04

申请号：US16830981

申请日：2020-03-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Anhao Cheng ,  Fang-Ting Kuo ,  Yen-Yu Chen

IPC: H01L23/522 ,  H01L23/528 ,  H01L49/02

Abstract: The present disclosure is directed to a method for the fabrication of MiM capacitor structures with metallic electrodes having nitrogen-rich metal nitride layers. The method includes depositing a first electrode bilayer on a first interconnect layer disposed on a substrate, where the first electrode bilayer includes a first layer and a second layer with a different nitrogen concentration. The method also includes depositing a dielectric layer on the first electrode bilayer and depositing a second electrode bilayer on the dielectric layer where the second electrode includes a third layer and a fourth layer with a different nitrogen concentration. The method further includes patterning the first electrode bilayer, the dielectric layer, and the second electrode bilayer to form a capacitor structure on the first interconnect layer.

公开(公告)号：US12166104B2

公开(公告)日：2024-12-10

申请号：US18357509

申请日：2023-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Anhao Cheng ,  Fang-Ting Kuo

IPC: H01L29/76 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/94 ,  H01L49/02 ,  H03K19/0185

Abstract: A method and structure providing a high-voltage transistor (HVT) including a gate dielectric, where at least part of the gate dielectric is provided within a trench disposed within a substrate. In some aspects, a gate oxide thickness may be controlled by way of a trench depth. By providing the HVT with a gate dielectric formed within a trench, embodiments of the present disclosure provide for the top gate stack surface of the HVT and the top gate stack surface of a low-voltage transistor (LVT), formed on the same substrate, to be substantially co-planar with each other, while providing a thick gate oxide for the HVTs. Further, because the top gate stack surface of HVT and the top gate stack surface of the LVT are substantially co-planar with each other, over polishing of the HVT gate stack can be avoided.

公开(公告)号：US12211890B2

公开(公告)日：2025-01-28

申请号：US17815524

申请日：2022-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Anhao Cheng ,  Fang-Ting Kuo ,  Yen-Yu Chen

IPC: H01L23/522 ,  H01L23/528 ,  H01L49/02

Abstract: The present disclosure is directed to a method for the fabrication of MiM capacitor structures with metallic electrodes having nitrogen-rich metal nitride layers. The method includes depositing a first electrode bilayer on a first interconnect disposed on a substrate, where the first electrode includes a first layer and a second layer with a different nitrogen concentration. The method also includes depositing a dielectric layer on the first electrode bilayer and depositing a second electrode bilayer on the first interconnect where the second electrode includes a third layer and a fourth layer with a different nitrogen concentration. The method further includes patterning the first electrode bilayer, the dielectric layer, and the second electrode bilayer to form a capacitor structure on the first interconnect layer.

公开(公告)号：US11978781B2

公开(公告)日：2024-05-07

申请号：US17459885

申请日：2021-08-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Anhao Cheng ,  Fang-Ting Kuo ,  Yen-Yu Chen

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/40 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/495 ,  H01L21/28176 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/823462 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/4238 ,  H01L29/518 ,  H01L29/66545 ,  H01L27/088 ,  H01L29/4975

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate containing a first active region in a first region of the substrate and a second active region in a second region of the substrate, a plurality of first gate structures over the first active region each including a first gate stack having a first high-k gate dielectric and a first gate electrode and first gate spacers surrounding the first gate stack, and a plurality of second gate structures over the second active region each including a second gate stack having a second high-k gate dielectric and a second gate electrode and second gate spacers surrounding the second gate stack. At least a portion of the second gate electrode comprises dopants.

公开(公告)号：US11955421B2

公开(公告)日：2024-04-09

申请号：US17461231

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Anhao Cheng

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/532

CPC classification number: H01L23/5223 ,  H01L21/76828 ,  H01L21/823475 ,  H01L23/53295 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76877 ,  H01L23/53228

Abstract: An integrated circuit includes a plurality of transistors and an interlevel dielectric layer formed over the transistors. The interlevel dielectric layer includes a first region and a second region with a higher dielectric constant than the first region. The difference in dielectric constant is produced by curing the first region shielding the second region from the curing. Metal signal lines are formed in the first region. Metal-on-metal capacitors are formed in the second region.

公开(公告)号：US11227935B2

公开(公告)日：2022-01-18

申请号：US16587003

申请日：2019-09-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Anhao Cheng ,  Fang-Ting Kuo

IPC: H01L29/76 ,  H01L29/94 ,  H01L29/66 ,  H01L21/8234 ,  H03K19/0185 ,  H01L27/092 ,  H01L49/02 ,  H01L21/8238

Abstract: A method and structure providing a high-voltage transistor (HVT) including a gate dielectric, where at least part of the gate dielectric is provided within a trench disposed within a substrate. In some aspects, a gate oxide thickness may be controlled by way of a trench depth. By providing the HVT with a gate dielectric formed within a trench, embodiments of the present disclosure provide for the top gate stack surface of the HVT and the top gate stack surface of a low-voltage transistor (LVT), formed on the same substrate, to be substantially co-planar with each other, while providing a thick gate oxide for the HVTs. Further, because the top gate stack surface of HVT and the top gate stack surface of the LVT are substantially co-planar with each other, over polishing of the HVT gate stack can be avoided.

公开(公告)号：US10431664B2

公开(公告)日：2019-10-01

申请号：US15884903

申请日：2018-01-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Anhao Cheng ,  Fang-Ting Kuo

IPC: H01L29/76 ,  H01L29/94 ,  H01L29/66 ,  H01L21/8234 ,  H03K19/0185 ,  H01L27/092 ,  H01L49/02 ,  H01L21/8238

Abstract: A method and structure providing a high-voltage transistor (HVT) including a gate dielectric, where at least part of the gate dielectric is provided within a trench disposed within a substrate. In some aspects, a gate oxide thickness may be controlled by way of a trench depth. By providing the HVT with a gate dielectric formed within a trench, embodiments of the present disclosure provide for the top gate stack surface of the HVT and the top gate stack surface of a low-voltage transistor (LVT), formed on the same substrate, to be substantially co-planar with each other, while providing a thick gate oxide for the HVTs. Further, because the top gate stack surface of HVT and the top gate stack surface of the LVT are substantially co-planar with each other, over polishing of the HVT gate stack can be avoided.