公开(公告)号：US20250112794A1

公开(公告)日：2025-04-03

申请号：US18981187

申请日：2024-12-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Lien Linus LU ,  Cheng-En LEE

IPC: H04L9/32 ,  G06F21/75 ,  G11C11/419 ,  H03K3/03

Abstract: Disclosed is a physical unclonable function generator circuit and method. In one embodiment, physical unclonable function (PUF) generator includes: a PUF cell array that comprises a plurality of bit cells, wherein each of the plurality of bit cells comprises at least two access transistors, at least one enable transistor, and at least two storage nodes, wherein the at least two storage nodes are pre-configured with substantially the same voltages allowing each of the plurality of bit cells having a first metastable logical state; a PUF control circuit coupled to the PUF cell array, wherein the PUF control circuit is configured to access the plurality of bit cells to determine second logical states by turning on the at least one enable transistor and turning off the at least two access transistors of each of the plurality of bit cells, and based on the second logical states of the plurality of bit cells, to generate a PUF output; and a noise injector coupled to the PUF control circuit and the PUF cell array, wherein the noise injector is configured to create stressed operation conditions to evaluate stability of the plurality of bit cells.

公开(公告)号：US20240154823A1

公开(公告)日：2024-05-09

申请号：US18412344

申请日：2024-01-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Lien Linus LU ,  Cheng-En LEE

IPC: H04L9/32 ,  G06F21/75

CPC classification number: H04L9/3278 ,  G06F21/75 ,  H03K3/0315

Abstract: Disclosed is a physical unclonable function generator circuit and method. In one embodiment, physical unclonable function (PUF) generator includes: a PUF cell array that comprises a plurality of bit cells, wherein each of the plurality of bit cells comprises at least two access transistors, at least one enable transistor, and at least two storage nodes, wherein the at least two storage nodes are pre-configured with substantially the same voltages allowing each of the plurality of bit cells having a first metastable logical state; a PUF control circuit coupled to the PUF cell array, wherein the PUF control circuit is configured to access the plurality of bit cells to determine second logical states by turning on the at least one enable transistor and turning off the at least two access transistors of each of the plurality of bit cells, and based on the second logical states of the plurality of bit cells, to generate a PUF output; and a noise injector coupled to the PUF control circuit and the PUF cell array, wherein the noise injector is configured to create stressed operation conditions to evaluate stability of the plurality of bit cells.

公开(公告)号：US20200058465A1

公开(公告)日：2020-02-20

申请号：US16539513

申请日：2019-08-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsiung LIN ,  Cheng-En LEE ,  Chia-Lin OU ,  Hsuan-Pang LIU ,  Yao-Jen YEH

IPC: H01J37/317 ,  H01J37/30 ,  H01J37/08

Abstract: The present disclosure relates to a method includes generating ions with an ion source of an ion implantation apparatus based on an ion implantation recipe. The method includes accelerating the generated ions based on an ion energy setting in the ion implantation recipe and determining an energy spectrum of the accelerated ions. The method also includes analyzing a relationship between the determined energy spectrum and the ion energy setting. The method further includes adjusting at least one parameter of a final energy magnet (FEM) of the ion implantation apparatus based on the analyzed relationship.

公开(公告)号：US20200043700A1

公开(公告)日：2020-02-06

申请号：US16525071

申请日：2019-07-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Hsiung LIN ,  Yao-Jen YEH ,  Chia-Lin OU ,  Cheng-En LEE ,  Hsuan-Pang LIU

IPC: H01J37/317 ,  H01L21/265 ,  H01L21/67

Abstract: A method of tuning an ion implantation apparatus is disclosed. The method includes operations of applying any wafer acceptance test (WAT) recipe to a test sample, calculating a recipe for a direct current (DC) final energy magnet (FEM), calculating a real energy of the DC FEM, verifying the tool energy shift, and obtaining a peak spectrum of the DC FEM.

公开(公告)号：US20190379381A1

公开(公告)日：2019-12-12

申请号：US16230088

申请日：2018-12-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Lien Linus LU ,  Cheng-En LEE ,  Jui-Che TSAI

IPC: H03K19/177 ,  G06F12/14 ,  G06F21/72 ,  H04L9/32 ,  G11C16/22

Abstract: Disclosed is a physical unclonable function generator circuit and method. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells, wherein each of the plurality of bit cells comprises at least two inverters, at least one floating capacitor, at least two dynamic nodes, wherein the at least one floating capacitor is coupled between a first inverter at a first dynamic node and a second inverter at a second dynamic node; a PUF controller coupled to the PUF cell array, wherein the PUF controller is configured to charge the first dynamic nodes through the respective first inverters in the plurality of bit cells; and a finite state machine coupled to the PUF cell array configured to determine voltage levels on the second dynamic nodes through the respective second inverters in the plurality of bit cells to determine first logical states of the plurality of bit cells at at least one sampling time and generate a PUF signature.