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公开(公告)号:US20200020584A1
公开(公告)日:2020-01-16
申请号:US16149597
申请日:2018-10-02
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Yi-Hsiung LIN , Yi-Hsun CHIU , Shang-Wen CHANG
IPC: H01L21/768 , H01L23/528 , H01L23/535 , H01L29/08 , H01L29/06 , H01L29/78 , H01L29/66
Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device structure includes a first epitaxial structure and a second epitaxial structure over a semiconductor substrate. The semiconductor device structure also includes a first conductive via electrically connected to the first epitaxial structure through a conductive contact. The first conductive via is misaligned with the first epitaxial structure. The semiconductor device structure further includes a second conductive via electrically connected to the second epitaxial structure. The second conductive via is aligned with the second epitaxial structure.
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公开(公告)号:US20220130757A1
公开(公告)日:2022-04-28
申请号:US17647572
申请日:2022-01-10
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Shang-Wen CHANG , Yi-Hsiung LIN
IPC: H01L23/522 , H01L29/78 , H01L21/8234 , H01L21/768 , H01L21/311 , H01L23/535 , H01L29/417 , H01L29/66
Abstract: A method and structure for forming a local interconnect, without routing the local interconnect through an overlying metal layer. In various embodiments, a first dielectric layer is formed over a gate stack of at least one device and a second dielectric layer is formed over a contact metal layer of the at least one device. In various embodiments, a selective etching process is performed to remove the second dielectric layer and expose the contact metal layer, without substantial removal of the first dielectric layer. In some examples, a metal VIA layer is deposited over the at least one device. The metal VIA layer contacts the contact metal layer and provides a local interconnect structure. In some embodiments, a multi-level interconnect network overlying the local interconnect structure is formed.
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公开(公告)号:US20200105603A1
公开(公告)日:2020-04-02
申请号:US16251642
申请日:2019-01-18
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Shang-Wen CHANG , Yi-Hsiung LIN , Yi-Hsun CHIU
IPC: H01L21/8234 , H01L29/66 , H01L29/78 , H01L21/768 , H01L27/088
Abstract: A method for forming a FinFET device structure includes forming a first fin structure and a second fin structure on a substrate. The method also includes depositing a first spacer layer over the first and second fin structures. The method also includes growing a power rail between the bottom portion of the first fin structure and the bottom portion of the second fin structure. The method also includes forming a second spacer layer over the sidewalls of the first spacer layer and over the top surface of the power rail. The method also includes forming a first fin isolation structure over the power rail between the first and second fin structures. The method also includes forming a first contact structure over the first fin structure and a portion of the power rail. The method also includes forming a second contact structure over the second fin structure.
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公开(公告)号:US20180350738A1
公开(公告)日:2018-12-06
申请号:US16047884
申请日:2018-07-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Shang-Wen CHANG , Yi-Hsiung LIN
IPC: H01L23/522 , H01L29/78 , H01L21/768 , H01L29/417 , H01L29/66 , H01L21/311 , H01L23/535
CPC classification number: H01L23/5226 , H01L21/31111 , H01L21/76895 , H01L21/823431 , H01L23/535 , H01L29/41791 , H01L29/66553 , H01L29/66795 , H01L29/785 , H01L29/7851
Abstract: A method and structure for forming a local interconnect, without routing the local interconnect through an overlying metal layer. In various embodiments, a first dielectric layer is formed over a gate stack of at least one device and a second dielectric layer is formed over a contact metal layer of the at least one device. In various embodiments, a selective etching process is performed to remove the second dielectric layer and expose the contact metal layer, without substantial removal of the first dielectric layer. In some examples, a metal VIA layer is deposited over the at least one device. The metal VIA layer contacts the contact metal layer and provides a local interconnect structure. In some embodiments, a multi-level interconnect network overlying the local interconnect structure is formed.
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公开(公告)号:US20190165177A1
公开(公告)日:2019-05-30
申请号:US16176072
申请日:2018-10-31
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chih-Liang CHEN , Chih-Ming LAI , Ching-Wei TSAI , Charles Chew-Yuen YOUNG , Jiann-Tyng TZENG , Kuo-Cheng CHING , Ru-Gun LIU , Wei-Hao WU , Yi-Hsiung LIN , Chia-Hao CHANG , Lei-Chun CHOU
IPC: H01L29/78 , H01L23/528 , H01L29/417 , H01L29/66 , H01L27/088
Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices. This isolation prevents electrical connection between the one or more metal rail conductors and the gate, the source, and/or the drain regions these various non-planar semiconductor devices.
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公开(公告)号:US20180061753A1
公开(公告)日:2018-03-01
申请号:US15253311
申请日:2016-08-31
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Shang-Wen CHANG , Yi-Hsiung LIN
IPC: H01L23/522 , H01L29/78 , H01L29/417 , H01L23/535 , H01L29/66 , H01L21/311 , H01L21/768
CPC classification number: H01L23/5226 , H01L21/31111 , H01L21/76895 , H01L21/823431 , H01L23/535 , H01L29/41791 , H01L29/66553 , H01L29/66795 , H01L29/785 , H01L29/7851
Abstract: A method and structure for forming a local interconnect, without routing the local interconnect through an overlying metal layer. In various embodiments, a first dielectric layer is formed over a gate stack of at least one device and a second dielectric layer is formed over a contact metal layer of the at least one device. In various embodiments, a selective etching process is performed to remove the second dielectric layer and expose the contact metal layer, without substantial removal of the first dielectric layer. In some examples, a metal VIA layer is deposited over the at least one device. The metal VIA layer contacts the contact metal layer and provides a local interconnect structure. In some embodiments, a multi-level interconnect network overlying the local interconnect structure is formed.
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公开(公告)号:US20230091869A1
公开(公告)日:2023-03-23
申请号:US18053021
申请日:2022-11-07
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chih-Liang CHEN , Chih-Ming LAI , Ching-Wei TSAI , Charles Chew-Yuen YOUNG , Jiann-Tyng TZENG , Kuo-Cheng CHIANG , Ru-Gun LIU , Wei-Hao WU , Yi-Hsiung LIN , Chia-Hao CHANG , Lei-Chun CHOU
IPC: H01L29/78 , H01L23/528 , H01L27/088 , H01L29/66 , H01L23/535 , H01L21/768 , H01L21/8234 , H01L23/48
Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices. This isolation prevents electrical connection between the one or more metal rail conductors and the gate, the source, and/or the drain regions these various non-planar semiconductor devices.
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公开(公告)号:US20220336455A1
公开(公告)日:2022-10-20
申请号:US17810341
申请日:2022-06-30
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Yi-Hsiung LIN , Yi-Hsun CHIU , Shang-Wen CHANG , Ching-Wei TSAI , Yu-Xuan HUANG , Kuan-Lun CHENG , Chih-Hao WANG
IPC: H01L27/092 , H01L29/78 , H01L29/66 , H01L29/76
Abstract: The present disclosure relates to an integrated circuit. In one implementation, the integrated circuit may include a semiconductor substrate; at least one source region comprising a first doped semiconductor material; at least one drain region comprising a second doped semiconductor material; at least one gate formed between the at least one source region and the at least one drain region; and a nanosheet formed between the semiconductor substrate and the at least one gate. The nanosheet may be configured as a routing channel for the at least one gate and may have a first region having a first width and a second region having a second width. The first width may be smaller than the second width.
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公开(公告)号:US20200294860A1
公开(公告)日:2020-09-17
申请号:US16889156
申请日:2020-06-01
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Shang-Wen CHANG , Yi-Hsiung LIN , Yi-Hsun CHIU
IPC: H01L21/8234 , H01L29/66 , H01L29/78 , H01L27/088 , H01L21/768
Abstract: A fin field effect transistor device structure includes a first fin structure formed on a substrate. The fin field effect transistor device structure also includes a spacer layer surrounding the first fin structure. The fin field effect transistor device structure further includes a power rail formed over the substrate besides a bottom portion of the first fin structure. The fin field effect transistor device structure further includes a first contact structure formed over the first fin structure and in contact with a portion of the power rail.
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公开(公告)号:US20210066291A1
公开(公告)日:2021-03-04
申请号:US16558010
申请日:2019-08-30
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Yi-Hsiung LIN , Yi-Hsun CHIU , Shang-Wen CHANG , Ching-Wei TSAI , Yu-Xuan HUANG , Kuan-Lun CHENG , Chih-Hao WANG
IPC: H01L27/092 , H01L29/76 , H01L29/66 , H01L29/78
Abstract: The present disclosure relates to an integrated circuit. In one implementation, the integrated circuit may include a semiconductor substrate; at least one source region comprising a first doped semiconductor material; at least one drain region comprising a second doped semiconductor material; at least one gate formed between the at least one source region and the at least one drain region; and a nanosheet formed between the semiconductor substrate and the at least one gate. The nanosheet may be configured as a routing channel for the at least one gate and may have a first region having a first width and a second region having a second width. The first width may be smaller than the second width.
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