公开(公告)号：US20200350404A1

公开(公告)日：2020-11-05

申请号：US16932924

申请日：2020-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Hsiung Tsai ,  Wei-Yuan Lu ,  Chien-Tai Chan ,  Wei-Yang Lee ,  Da-Wen Lin

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/02 ,  H01L29/16 ,  H01L29/32 ,  H01L29/04 ,  H01L29/06 ,  H01L29/165

Abstract: Embodiments of mechanisms for forming dislocations in source and drain regions of finFET devices are provided. The mechanisms involve recessing fins and removing the dielectric material in the isolation structures neighboring fins to increase epitaxial regions for dislocation formation. The mechanisms also involve performing a pre-amorphous implantation (PAI) process either before or after the epitaxial growth in the recessed source and drain regions. An anneal process after the PAI process enables consistent growth of the dislocations in the source and drain regions. The dislocations in the source and drain regions (or stressor regions) can form consistently to produce targeted strain in the source and drain regions to improve carrier mobility and device performance for NMOS devices.

公开(公告)号：US10224245B2

公开(公告)日：2019-03-05

申请号：US15076762

申请日：2016-03-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Pin Lin ,  Chien-Tai Chan ,  Hsien-Chin Lin ,  Shyue-Shyh Lin

IPC: H01L29/76 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/165

Abstract: A method includes forming first and second fins of a finFET extending above a semiconductor substrate, with a shallow trench isolation (STI) region in between, and a distance between a top surface of the STI region and top surfaces of the first and second fins. First and second fin extensions are provided on top and side surfaces of the first and second fins above the top surface of the STI region. Material is removed from the STI region, to increase the distance between the top surface of the STI region and top surfaces of the first and second fins. A conformal stressor dielectric material is deposited over the fins and STI region. The conformal dielectric stressor material is reflowed, to flow into a space between the first and second fins above a top surface of the STI region, to apply stress to a channel of the finFET.

公开(公告)号：US10665717B2

公开(公告)日：2020-05-26

申请号：US16112766

申请日：2018-08-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Hsiung Tsai ,  Chien-Tai Chan ,  Ziwei Fang ,  Kei-Wei Chen ,  Huai-Tei Yang

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/223 ,  H01L21/265 ,  H01L21/285 ,  H01L21/768

Abstract: A FinFET device and a method of forming the same are disclosed. In accordance with some embodiments, a FinFET device includes a substrate having at least one fin, a gate stack across the at least one fin, a strained layer aside the gate stack and a silicide layer over the strained layer. The strained layer has a boron surface concentration greater than about 2E20 atom/cm3 within a depth range of about 0-5 nm from a surface of the strained layer.

公开(公告)号：US10062780B2

公开(公告)日：2018-08-28

申请号：US15652271

申请日：2017-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Hsiung Tsai ,  Chien-Tai Chan ,  Ziwei Fang ,  Kei-Wei Chen ,  Huai-Tei Yang

IPC: H01L29/78 ,  H01L21/223 ,  H01L21/265 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/2236 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/76897 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/785

Abstract: A FinFET device and a method of forming the same are disclosed. In accordance with some embodiments, a FinFET device includes a substrate having at least one fin, a gate stack across the at least one fin, a strained layer aside the gate stack and a silicide layer over the strained layer. The strained layer has a boron surface concentration greater than about 2E20 atom/cm3 within a depth range of about 0-5 nm from a surface of the strained layer.

公开(公告)号：US09508556B1

公开(公告)日：2016-11-29

申请号：US15009828

申请日：2016-01-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Hsiung Tsai ,  Chien-Tai Chan ,  Ziwei Fang ,  Kei-Wei Chen

IPC: H01L29/66 ,  H01L21/30 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L29/7848 ,  H01J37/3244 ,  H01J37/32449 ,  H01L21/3065 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/0886 ,  H01L29/66636 ,  H01L29/785

Abstract: A method for fabricating a fin field effect transistor (FinFET) is provided. The method includes steps as follows. A gate stack is formed over a substrate having a semiconductor fin. Recesses are formed in the semiconductor fin beside the gate stack. A pre-clean process is performed to remove native oxides on surfaces of the recesses. After the pre-clean process, a selectivity proximity push process is performed using a fluorine-containing gas and a first hydrogen gas to the recesses. Strained layers are formed in the recesses.

Abstract translation: 提供了制造鳍式场效应晶体管（FinFET）的方法。 该方法包括以下步骤。 在具有半导体鳍片的衬底上形成栅叠层。 在栅堆叠旁边的半导体鳍形成凹部。 执行预清洁处理以去除凹部表面上的天然氧化物。 在预清洁处理之后，使用含氟气体和第一氢气对凹部进行选择性接近推动过程。 应变层形成在凹部中。

公开(公告)号：US20200381529A1

公开(公告)日：2020-12-03

申请号：US16994865

申请日：2020-08-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hsiung Tsai ,  Kuo-Feng Yu ,  Chien-Tai Chan ,  Ziwei Fang ,  Kei-Wei Chen ,  Huai-Tei Yang

IPC: H01L29/49 ,  H01L21/225 ,  H01L29/66 ,  H01L29/78

Abstract: A gate structure, a semiconductor device, and the method of forming a semiconductor device are provided. In various embodiments, the gate structure includes a gate stack and a doped spacer overlying a sidewall of the gate stack. The gate stack contains a doped work function metal (WFM) stack and a metal gate electrode overlying the doped WFM stack.

公开(公告)号：US10276715B2

公开(公告)日：2019-04-30

申请号：US15054104

申请日：2016-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Hsiung Tsai ,  Chien-Tai Chan ,  Kuo-Feng Yu ,  Kei-Wei Chen

IPC: H01L29/76 ,  H01L29/78 ,  H01L29/66 ,  H01L21/306

Abstract: A fin field effect transistor (FinFET) is provided. The FinFET includes a substrate, a gate stack, and strained source and drain regions. The substrate has a semiconductor fin. The gate stack is disposed across the semiconductor fin. Moreover, the strained source and drain regions are located within recesses of the semiconductor fin beside the gate stack. Moreover, at least one of the strained source and drain regions has a top portion and a bottom portion, the bottom portion is connected to the top portion, and a bottom width of the top portion is greater than a top width of the bottom portion.

公开(公告)号：US20170323971A1

公开(公告)日：2017-11-09

申请号：US15652271

申请日：2017-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Hsiung Tsai ,  Chien-Tai Chan ,  Ziwei Fang ,  Kei-Wei Chen ,  Huai-Tei Yang

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/223 ,  H01L21/265

CPC classification number: H01L29/7848 ,  H01L21/2236 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/7834 ,  H01L29/785

Abstract: A FinFET device and a method of forming the same are disclosed. In accordance with some embodiments, a FinFET device includes a substrate having at least one fin, a gate stack across the at least one fin, a strained layer aside the gate stack and a silicide layer over the strained layer. The strained layer has a boron surface concentration greater than about 2E20 atom/cm3 within a depth range of about 0-5 nm from a surface of the strained layer.

公开(公告)号：US20170222051A1

公开(公告)日：2017-08-03

申请号：US15009834

申请日：2016-01-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Hsiung Tsai ,  Chien-Tai Chan ,  Ziwei Fang ,  Kei-Wei Chen ,  Huai-Tei Yang

IPC: H01L29/78 ,  H01L21/223 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L29/7848 ,  H01L21/2236 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/7834 ,  H01L29/785

Abstract: A FinFET device and a method of forming the same are disclosed. In accordance with some embodiments, a FinFET device includes a substrate having at least one fin, a gate stack across the at least one fin, a strained layer aside the gate stack and a silicide layer over the strained layer. The strained layer has a boron surface concentration greater than about 2E20 atom/cm3 within a depth range of about 0-5 nm from a surface of the strained layer.

公开(公告)号：US09224737B2

公开(公告)日：2015-12-29

申请号：US14554179

申请日：2014-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Kai Chen ,  Hsien-Hsin Lin ,  Chia-Pin Lin ,  Chien-Tai Chan ,  Yuan-Ching Peng

IPC: H01L27/12 ,  H01L27/092 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7853

Abstract: A method includes forming a first fin and a second fin extending above a semiconductor substrate, with a shallow trench isolation (STI) region between them. A space is defined between the first and second fins above a top surface of the STI region. A first height is defined between the top surface of the STI region and top surfaces of the first and second fins. A flowable dielectric material is deposited into the space. The dielectric material has a top surface above the top surface of the STI region, so as to define a second height between the top surface of the dielectric material and the top surfaces of the first and second fins. The second height is less than the first height. First and second fin extensions are epitaxially formed above the dielectric, on the first and second fins, respectively, after the depositing step.