公开(公告)号：US20240379448A1

公开(公告)日：2024-11-14

申请号：US18783632

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Han Tsai ,  Chung-Chiang Wu ,  Cheng-Lung Hung ,  Weng Chang ,  Chi On Chui

IPC: H01L21/8234 ,  H01L21/28 ,  H01L27/088 ,  H01L29/49

Abstract: A method includes forming a gate dielectric on a semiconductor region, depositing a work-function layer over the gate dielectric, depositing a silicon layer over the work-function layer, and depositing a glue layer over the silicon layer. The work-function layer, the silicon layer, and the glue layer are in-situ deposited. The method further includes depositing a filling-metal over the glue layer; and performing a planarization process, wherein remaining portions of the glue layer, the silicon layer, and the work-function layer form portions of a gate electrode.

公开(公告)号：US12040235B2

公开(公告)日：2024-07-16

申请号：US17870343

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ching Lee ,  Hsin-Han Tsai ,  Shih-Hang Chiu ,  Tsung-Ta Tang ,  Chung-Chiang Wu ,  Hung-Chin Chung ,  Hsien-Ming Lee ,  Da-Yuan Lee ,  Jian-Hao Chen ,  Chien-Hao Chen ,  Kuo-Feng Yu ,  Chia-Wei Chen ,  Chih-Yu Hsu

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/40 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L21/82345 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/66545

Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.

公开(公告)号：US11961732B2

公开(公告)日：2024-04-16

申请号：US17814716

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ching Lee ,  Chung-Chiang Wu ,  Shih-Hang Chiu ,  Hsuan-Yu Tung ,  Da-Yuan Lee

IPC: H01L21/02 ,  H01L21/768 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L21/02175 ,  H01L21/76841 ,  H01L21/76871 ,  H01L27/0886 ,  H01L29/66871

Abstract: A method includes depositing a first work-function layer and a second work-function layer in a first device region and a second device region, respectively, and depositing a first fluorine-blocking layer and a second fluorine-blocking layer in the first device region and the second device region, respectively. The first fluorine-blocking layer is over the first work-function layer, and the second fluorine-blocking layer is over the second work-function layer. The method further includes removing the second fluorine-blocking layer, and forming a first metal-filling layer over the first fluorine-blocking layer, and a second metal-filling layer over the second work-function layer.

公开(公告)号：US11728341B2

公开(公告)日：2023-08-15

申请号：US17656295

申请日：2022-03-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Wu ,  Shih-Hang Chiu ,  Chih-Chang Hung ,  I-Wei Yang ,  Shu-Yuan Ku ,  Cheng-Lung Hung ,  Da-Yuan Lee ,  Ching-Hwanq Su

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H10B10/00

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/66545 ,  H10B10/12

Abstract: A method includes forming a first semiconductor fin in a substrate, forming a metal gate structure over the first semiconductor fin, removing a portion of the metal gate structure to form a first recess in the metal gate structure that is laterally separated from the first semiconductor fin by a first distance, wherein the first distance is determined according to a first desired threshold voltage associated with the first semiconductor fin, and filling the recess with a dielectric material.

公开(公告)号：US11594610B2

公开(公告)日：2023-02-28

申请号：US17165142

申请日：2021-02-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hang Chiu ,  Chung-Chiang Wu ,  Jo-Chun Hung ,  Wei-Cheng Wang ,  Kuan-Ting Liu ,  Chi On Chui

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/66

Abstract: Semiconductor devices having improved gate electrode structures and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a gate structure over a semiconductor substrate, the gate structure including a high-k dielectric layer; an n-type work function layer over the high-k dielectric layer; an anti-reaction layer over the n-type work function layer, the anti-reaction layer including a dielectric material; a p-type work function layer over the anti-reaction layer, the p-type work function layer covering top surfaces of the anti-reaction layer; and a conductive cap layer over the p-type work function layer.

公开(公告)号：US11532509B2

公开(公告)日：2022-12-20

申请号：US16884837

申请日：2020-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Wu ,  Po-Cheng Chen ,  Kuo-Chan Huang ,  Pin-Hsuan Yeh ,  Wei-Chin Lee ,  Hsien-Ming Lee ,  Chien-Hao Chen ,  Chi On Chui

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/423

Abstract: A method includes forming a gate electrode on a semiconductor region, recessing the gate electrode to generate a recess, performing a first deposition process to form a first metallic layer on the gate electrode and in the recess, wherein the first deposition process is performed using a first precursor, and performing a second deposition process to form a second metallic layer on the first metallic layer using a second precursor different from the first precursor. The first metallic layer and the second metallic layer comprise a same metal. The method further incudes forming a dielectric hard mask over the second metallic layer, and forming a gate contact plug penetrating through the dielectric hard mask. The gate contact plug contacts a top surface of the second metallic layer.

公开(公告)号：US20220367263A1

公开(公告)日：2022-11-17

申请号：US17869462

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Wu ,  Hsueh Wen Tsau ,  Chia-Ching Lee ,  Cheng-Lung Hung ,  Ching-Hwanq Su

IPC: H01L21/768 ,  H01L29/66 ,  H01L23/532 ,  H01L29/78 ,  H01L23/535

Abstract: A method includes forming an opening in a dielectric layer, depositing a seed layer in the opening, wherein first portions of the seed layer have a first concentration of impurities, exposing the first portions of the seed layer to a plasma, wherein after exposure to the plasma the first portions have a second concentration of impurities that is less than the first concentration of impurities, and filling the opening with a conductive material to form a conductive feature. In an embodiment, the seed layer includes tungsten, and the conductive material includes tungsten. In an embodiment, the impurities include boron.

公开(公告)号：US20220367261A1

公开(公告)日：2022-11-17

申请号：US17813806

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing CO., Ltd.

Inventor： Chung-Chiang Wu ,  Po-Cheng Chen ,  Kuo-Chan Huang ,  Pin-Hsuan Yeh ,  Wei-Chin Lee ,  Hsien-Ming Lee ,  Chien-Hao Chen ,  Chi On Chui

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/423

Abstract: A method includes forming a gate electrode on a semiconductor region, recessing the gate electrode to generate a recess, performing a first deposition process to form a first metallic layer on the gate electrode and in the recess, wherein the first deposition process is performed using a first precursor, and performing a second deposition process to form a second metallic layer on the first metallic layer using a second precursor different from the first precursor. The first metallic layer and the second metallic layer comprise a same metal. The method further incudes forming a dielectric hard mask over the second metallic layer, and forming a gate contact plug penetrating through the dielectric hard mask. The gate contact plug contacts a top surface of the second metallic layer.

公开(公告)号：US20220216201A1

公开(公告)日：2022-07-07

申请号：US17656295

申请日：2022-03-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Wu ,  Shih-Hang Chiu ,  Chih-Chang Hung ,  I-Wei Yang ,  Shu-Yuan Ku ,  Cheng-Lung Hung ,  Da-Yuan Lee ,  Ching-Hwanq Su

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/11 ,  H01L29/06

Abstract: A method includes forming a first semiconductor fin in a substrate, forming a metal gate structure over the first semiconductor fin, removing a portion of the metal gate structure to form a first recess in the metal gate structure that is laterally separated from the first semiconductor fin by a first distance, wherein the first distance is determined according to a first desired threshold voltage associated with the first semiconductor fin, and filling the recess with a dielectric material.

公开(公告)号：US20210391219A1

公开(公告)日：2021-12-16

申请号：US16900439

申请日：2020-06-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ching Lee ,  Hsin-Han Tsai ,  Shih-Hang Chiu ,  Tsung-Ta Tang ,  Chung-Chiang Wu ,  Hung-Chin Chung ,  Hsien-Ming Lee ,  Da-Yuan Lee ,  Jian-Hao Chen ,  Chien-Hao Chen ,  Kuo-Feng Yu ,  Chia-Wei Chen ,  Chih-Yu Hsu

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/40 ,  H01L27/088

Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.