公开(公告)号：US12218130B2

公开(公告)日：2025-02-04

申请号：US18526290

申请日：2023-12-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chang Hung ,  Chia-Jen Chen ,  Ming-Ching Chang ,  Shu-Yuan Ku ,  Yi-Hsuan Hsiao ,  I-Wei Yang

IPC: H01L27/088 ,  H01L21/28 ,  H01L21/283 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/321

Abstract: Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.

公开(公告)号：US20220359510A1

公开(公告)日：2022-11-10

申请号：US17872417

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chang Hung ,  Chia-Jen Chen ,  Ming-Ching Chang ,  Shu-Yuan Ku ,  Yi-Hsuan Hsiao ,  I-Wei Yang

IPC: H01L27/088 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L21/283 ,  H01L29/78

Abstract: Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.

公开(公告)号：US11289480B2

公开(公告)日：2022-03-29

申请号：US17000632

申请日：2020-08-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Wu ,  Shih-Hang Chiu ,  Chih-Chang Hung ,  I-Wei Yang ,  Shu-Yuan Ku ,  Cheng-Lung Hung ,  Da-Yuan Lee ,  Ching-Hwanq Su

IPC: H01L27/088 ,  H01L29/06 ,  H01L27/11 ,  H01L21/8234 ,  H01L29/66

Abstract: A method includes forming a first semiconductor fin in a substrate, forming a metal gate structure over the first semiconductor fin, removing a portion of the metal gate structure to form a first recess in the metal gate structure that is laterally separated from the first semiconductor fin by a first distance, wherein the first distance is determined according to a first desired threshold voltage associated with the first semiconductor fin, and filling the recess with a dielectric material.

公开(公告)号：US09478431B2

公开(公告)日：2016-10-25

申请号：US14967741

申请日：2015-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Kuei Liu ,  Teng-Chun Tsai ,  Kuo-Yin Lin ,  Shen-Nan Lee ,  Yu-Wei Chou ,  Kuo-Cheng Lien ,  Chang-Sheng Lin ,  Chih-Chang Hung ,  Yung-Cheng Lu

IPC: H01L21/3105 ,  H01L29/66 ,  H01L21/28 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/308 ,  H01L29/06

CPC classification number: H01L21/31055 ,  H01L21/02282 ,  H01L21/28123 ,  H01L21/3086 ,  H01L21/31058 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/0692 ,  H01L29/66545 ,  H01L29/66795

Abstract: The present disclosure provides a method of manufacturing an integrated circuit device in some embodiments. In the method, a semiconductor substrate is processed through a series of operations to form a topographically variable surface over the semiconductor substrate. The topographically variable surface varies in height across the semiconductor substrate. A polymeric bottom anti-reflective coating (BARC) is provided over the topographically variable surface. Chemical mechanical polishing is performed to remove a first portion of the BARC, and etching effectuates a top-down recessing of the BARC.

Abstract translation: 本公开提供了在一些实施例中制造集成电路器件的方法。 在该方法中，通过一系列操作来处理半导体衬底，以在半导体衬底上形成拓扑可变表面。 地形可变表面在半导体衬底上的高度变化。 在地形可变表面上提供聚合物底部抗反射涂层（BARC）。 执行化学机械抛光以去除BARC的第一部分，并且蚀刻实现BARC的自上而下的凹陷。

公开(公告)号：US20250126883A1

公开(公告)日：2025-04-17

申请号：US18991919

申请日：2024-12-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chang Hung ,  Chia-Jen Chen ,  Ming-Ching Chang ,  Shu-Yuan Ku ,  Yi-Hsuan Hsiao ,  I-Wei Yang

IPC: H10D84/83 ,  H01L21/02 ,  H01L21/283 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/762 ,  H10D30/60 ,  H10D62/00 ,  H10D62/10 ,  H10D62/13 ,  H10D64/01 ,  H10D64/27 ,  H10D64/66 ,  H10D84/01 ,  H10D84/03

Abstract: Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.

公开(公告)号：US20230387112A1

公开(公告)日：2023-11-30

申请号：US18359492

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jen-Chih Hsueh ,  Chih-Chang Hung ,  Tsung Fan Yin ,  Yi-Wei Chiu

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L29/66545 ,  H01L21/32135 ,  H01L21/31116 ,  H01L21/0217 ,  H01L21/823481 ,  H01L29/66492

Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in a substrate, the first semiconductor fin adjacent the second semiconductor fin, forming a dummy gate structure extending over the first semiconductor fin and the second semiconductor fin, depositing a first dielectric material surrounding the dummy gate structure, replacing the dummy gate structure with a first metal gate structure, performing an etching process on the first metal gate structure and on the first dielectric material to form a first recess in the first metal gate structure and a second recess in the first dielectric material, wherein the first recess extends into the substrate, and wherein the second recess is disposed between the first semiconductor fin and the second semiconductor fin, and depositing a second dielectric material within the first recess.

公开(公告)号：US11637206B2

公开(公告)日：2023-04-25

申请号：US17247687

申请日：2020-12-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Wei Yang ,  Chih-Chang Hung ,  Shu-Yuan Ku ,  Ryan Chia-Jen Chen ,  Ming-Ching Chang

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L27/088 ,  H01L23/532 ,  H01L29/66 ,  H01L21/033 ,  H01L21/8238 ,  H01L21/3213 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/311

Abstract: A semiconductor device and method of forming thereof includes a first fin and a second fin each extending from a substrate. A first gate segment is disposed over the first fin and a second gate segment is disposed over the second fin. An interlayer dielectric (ILD) layer is adjacent the first gate segment and the second gate segment. A cut region (e.g., opening or gap between first gate structure and the second gate structure) extends between the first and second gate segments. The cut region has a first portion has a first width and a second portion has a second width, the second width is greater than the first width. The second portion interposes the first and second gate segments and the first portion is defined within the ILD layer.

公开(公告)号：US20220359505A1

公开(公告)日：2022-11-10

申请号：US17869487

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jen-Chih Hsueh ,  Chih-Chang Hung ,  Tsung Fan Yin ,  Yi-Wei Chiu

IPC: H01L27/088 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8234 ,  H01L29/66

Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in a substrate, the first semiconductor fin adjacent the second semiconductor fin, forming a dummy gate structure extending over the first semiconductor fin and the second semiconductor fin, depositing a first dielectric material surrounding the dummy gate structure, replacing the dummy gate structure with a first metal gate structure, performing an etching process on the first metal gate structure and on the first dielectric material to form a first recess in the first metal gate structure and a second recess in the first dielectric material, wherein the first recess extends into the substrate, and wherein the second recess is disposed between the first semiconductor fin and the second semiconductor fin, and depositing a second dielectric material within the first recess.

公开(公告)号：US11011385B2

公开(公告)日：2021-05-18

申请号：US15686922

申请日：2017-08-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Kuei Liu ,  Teng-Chun Tsai ,  Kuo-Yin Lin ,  Shen-Nan Lee ,  Yu-Wei Chou ,  Kuo-Cheng Lien ,  Chang-Sheng Lin ,  Chih-Chang Hung ,  Yung-Cheng Lu

IPC: H01L21/3105 ,  H01L21/84 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/027 ,  H01L21/311 ,  H01L21/8238 ,  H01L29/66

Abstract: A method of manufacturing an integrated circuit device is provided. A first feature, which has a first susceptibility to damage by chemical mechanical processing (CMP), is formed at a first height as measured from an upper surface of the substrate. A second feature, which has a second susceptibility to damage by the CMP, is formed at a second height as measured from the upper surface of the substrate and is laterally spaced from the first feature by a recess. The second height is greater than the first height, and the second susceptibility is less than the first susceptibility. A sacrificial coating is formed in the recess over an uppermost surface of the first feature. CMP is performed to remove a first portion of the sacrificial coating and expose an upper surface of the second feature while leaving a second portion of the sacrificial coating in place over the first feature.

公开(公告)号：US10461171B2

公开(公告)日：2019-10-29

申请号：US15965183

申请日：2018-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsuan Hsiao ,  Shu-Yuan Ku ,  Chih-Chang Hung ,  I-Wei Yang ,  Chih-Ming Sun

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L29/06

Abstract: A method for forming a semiconductor device structure includes forming a first dummy gate stack and a second dummy gate stack over a semiconductor substrate and forming a dielectric layer over the semiconductor substrate to surround the first dummy gate stack and the second dummy gate stack. The method includes removing the first dummy gate stack and the second dummy gate stack to form a first trench and a second trench in the dielectric layer and removing the first dummy gate stack and the second dummy gate stack to form a first trench and a second trench in the dielectric layer. The method includes partially removing the first metal gate stack, the second metal gate stack, and the dielectric layer to form a recess. The method includes forming an insulating structure to partially or completely fill the recess.