公开(公告)号：US20240250089A1

公开(公告)日：2024-07-25

申请号：US18627692

申请日：2024-04-05

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Harry-Hak-Lay Chuang ,  Wei-Cheng Wu ,  Chien Hung Liu ,  Hsin Fu Lin ,  Hsien Jung Chen ,  Henry Wang ,  Tsung-Hao Yeh ,  Kuo-Ching Huang

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/84 ,  H01L29/66

CPC classification number: H01L27/1203 ,  H01L21/76251 ,  H01L21/76283 ,  H01L21/84 ,  H01L29/66772

Abstract: A layer stack including a first bonding dielectric material layer, a dielectric metal oxide layer, and a second bonding dielectric material layer is formed over a top surface of a substrate including a substrate semiconductor layer. A conductive material layer is formed by depositing a conductive material over the second bonding dielectric material layer. The substrate semiconductor layer is thinned by removing portions of the substrate semiconductor layer that are distal from the layer stack, whereby a remaining portion of the substrate semiconductor layer includes a top semiconductor layer. A semiconductor device may be formed on the top semiconductor layer.

公开(公告)号：US20240274716A1

公开(公告)日：2024-08-15

申请号：US18324238

申请日：2023-05-26

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Hsin Fu Lin ,  Shiang-Hung Huang ,  Pei-Shan Hsieh

IPC: H01L29/78 ,  H01L21/265 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/26506 ,  H01L29/0649 ,  H01L29/086 ,  H01L29/1041 ,  H01L29/42368 ,  H01L29/66689 ,  H01L29/66803

Abstract: A field effect transistor includes a source-side doped well, a drift-region well, a source region, a drain region; a shallow trench isolation structure including a first portion overlying the drift-region well and laterally spaced from the source-side doped well; a gate dielectric layer; a gate electrode overlying the gate dielectric layer; and a proximal doped layer stack embedded within the drift-region well and interposed between the source-side doped well and the first portion of the shallow trench isolation structure. Proximal doped semiconductor layers of the proximal doped layer stack have different average atomic concentrations of dopants of the second conductivity type.

公开(公告)号：US11978740B2

公开(公告)日：2024-05-07

申请号：US17674348

申请日：2022-02-17

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Harry-Hak-Lay Chuang ,  Kuo-Ching Huang ,  Wei-Cheng Wu ,  Hsin Fu Lin ,  Henry Wang ,  Chien Hung Liu ,  Tsung-Hao Yeh ,  Hsien Jung Chen

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/84 ,  H01L29/66

CPC classification number: H01L27/1203 ,  H01L21/76251 ,  H01L21/76283 ,  H01L21/84 ,  H01L29/66772

Abstract: A layer stack including a first bonding dielectric material layer, a dielectric metal oxide layer, and a second bonding dielectric material layer is formed over a top surface of a substrate including a substrate semiconductor layer. A conductive material layer is formed by depositing a conductive material over the second bonding dielectric material layer. The substrate semiconductor layer is thinned by removing portions of the substrate semiconductor layer that are distal from the layer stack, whereby a remaining portion of the substrate semiconductor layer includes a top semiconductor layer. A semiconductor device may be formed on the top semiconductor layer.