公开(公告)号：US20240389483A1

公开(公告)日：2024-11-21

申请号：US18317118

申请日：2023-05-15

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Yu-Wei Ting ,  Harry-Hak-Lay Chuang ,  Kuo-Pin Chang ,  Kuo-Ching Huang

IPC: H10N70/00 ,  H10N70/20

Abstract: An embodiment phase change material (PCM) switch may include a phase change material element, a first electrode, a second electrode, and a direct heating element including an ionic resistance change material contacting the phase change material element. The phase change material element may include a phase change material that switches from an electrically conducting phase to an electrically insulating phase or from an electrically insulating phase to an electrically conducting phase by application of a heat pulse generated by the heating element. The PCM switch may further include a switching electrode contacting the ionic resistance change material such that the ionic resistance change material may be switched from a high resistance to a low resistance state by application of voltages to the first electrode, the second electrode, and the switching electrode. Electrical currents within the ionic resistance change material may generate heat that switches the phase change material element.

公开(公告)号：US20240387399A1

公开(公告)日：2024-11-21

申请号：US18317994

申请日：2023-05-16

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Fu-Hai Li ,  Chien Hung Liu ,  Hsien Jung Chen ,  Kuo-Ching Huang ,  Harry-Hak-Lay Chuang

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522

Abstract: A semiconductor may include a handle substrate, a semiconductor material layer on which semiconductor devices, metal interconnect structures, dielectric material layers, and an inductor structure are located, and a patterned magnetic shielding layer including at least one portion of a ferromagnetic material having relative permeability of at least 20 and disposed between the semiconductor material layer and the handle substrate and reducing electromagnetic coupling between the inductor structure and the handle substrate.

公开(公告)号：US20240250089A1

公开(公告)日：2024-07-25

申请号：US18627692

申请日：2024-04-05

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Harry-Hak-Lay Chuang ,  Wei-Cheng Wu ,  Chien Hung Liu ,  Hsin Fu Lin ,  Hsien Jung Chen ,  Henry Wang ,  Tsung-Hao Yeh ,  Kuo-Ching Huang

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/84 ,  H01L29/66

CPC classification number: H01L27/1203 ,  H01L21/76251 ,  H01L21/76283 ,  H01L21/84 ,  H01L29/66772

Abstract: A layer stack including a first bonding dielectric material layer, a dielectric metal oxide layer, and a second bonding dielectric material layer is formed over a top surface of a substrate including a substrate semiconductor layer. A conductive material layer is formed by depositing a conductive material over the second bonding dielectric material layer. The substrate semiconductor layer is thinned by removing portions of the substrate semiconductor layer that are distal from the layer stack, whereby a remaining portion of the substrate semiconductor layer includes a top semiconductor layer. A semiconductor device may be formed on the top semiconductor layer.

公开(公告)号：US11621248B2

公开(公告)日：2023-04-04

申请号：US17218401

申请日：2021-03-31

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Harry-Hak-Lay Chuang ,  Wen-Tuo Huang ,  Wei Cheng Wu

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L21/66 ,  H01L25/00

Abstract: Bonded wafer device structures, such as a wafer-on-wafer (WoW) structures, and methods of fabricating bonded wafer device structures, including an array of contact pads formed in an interconnect level of at least one wafer of the bonded wafer device structure. The array of contact pads formed in an interconnect level of at least one wafer may have an array pattern that corresponds to an array pattern of contact pads that is subsequently formed over a surface of the bonded wafer structure. The array of contact pads formed in an interconnect level of at least one wafer of the bonded wafer device structure may enable improved testing of individual wafers, including circuit probe testing, prior to the wafer being stacked and bonded to one or more additional wafers to form a bonded wafer structure.

公开(公告)号：US11158546B2

公开(公告)日：2021-10-26

申请号：US16695071

申请日：2019-11-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Chin-Yi Huang ,  Shih-Chang Liu

IPC: H01L21/82 ,  H01L29/788 ,  H01L21/8238

Abstract: A semiconductor arrangement is provided comprising a guard region. The semiconductor arrangement comprises an active region disposed on a first side of the guard region. The active region comprises an active device. The guard region of the semiconductor arrangement comprises residue from the active region. A method of forming a semiconductor arrangement is also provided.

公开(公告)号：US10748895B2

公开(公告)日：2020-08-18

申请号：US15611989

申请日：2017-06-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Shih-Chang Liu ,  Ming Chyi Liu

IPC: H01L27/088 ,  H01L27/11521 ,  H01L29/66 ,  H01L29/788 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/28

Abstract: A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a first gate structure on a first side of an active area and a second gate structure on a second side of the active area, where the first gate structure and the second gate structure share the active area. A method of forming the semiconductor arrangement includes forming a deep implant of the active area before forming the first gate structure, and then forming a shallow implant of the active area. Forming the deep implant prior to forming the first gate structure alleviates the need for an etching process that degrades the first gate structure. The first gate structure thus has a desired configuration and is able to be formed closer to other gate structures to enhance device density.

公开(公告)号：US09673194B2

公开(公告)日：2017-06-06

申请号：US14097516

申请日：2013-12-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Shih-Chang Liu ,  Ming Chyi Liu

IPC: H01L27/088 ,  H01L21/265 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/66 ,  H01L29/06 ,  H01L21/28 ,  H01L29/788 ,  H01L27/11521

CPC classification number: H01L27/088 ,  H01L21/28273 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823481 ,  H01L27/11521 ,  H01L29/6656 ,  H01L29/66825 ,  H01L29/7883

Abstract: A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a first gate structure on a first side of an active area and a second gate structure on a second side of the active area, where the first gate structure and the second gate structure share the active area. A method of forming the semiconductor arraignment includes forming a deep implant of the active area before forming the first gate structure, and then forming a shallow implant of the active area. Forming the deep implant prior to forming the first gate structure alleviates the need for an etching process that degrades the first gate structure. The first gate structure thus has a desired configuration and is able to be formed closer to other gate structures to enhance device density.

公开(公告)号：US20240222332A1

公开(公告)日：2024-07-04

申请号：US18604542

申请日：2024-03-14

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Harry-Hak-Lay Chuang ,  Wei-Cheng Wu ,  Wen-Tuo Huang

IPC: H01L25/065 ,  H01L21/66 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L22/12 ,  H01L22/32 ,  H01L23/481 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/05147 ,  H01L2224/08145 ,  H01L2224/8083 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06541 ,  H01L2225/06596

Abstract: Bonded wafer device structures, such as a wafer-on-wafer (WoW) structures, and methods of fabricating bonded wafer device structures, including an array of contact pads formed in an interconnect level of at least one wafer of the bonded wafer device structure. The array of contact pads formed in an interconnect level of at least one wafer may have an array pattern that corresponds to an array pattern of contact pads that is subsequently formed over a surface of the bonded wafer structure. The array of contact pads formed in an interconnect level of at least one wafer of the bonded wafer device structure may enable improved testing of individual wafers, including circuit probe testing, prior to the wafer being stacked and bonded to one or more additional wafers to form a bonded wafer structure.

公开(公告)号：US20220291306A1

公开(公告)日：2022-09-15

申请号：US17470545

申请日：2021-09-09

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Cheng-Wei Chien ,  Harry-Hak-Lay Chuang ,  Kuei-Hung Shen ,  Kuo-Feng Huang ,  Bo-Hung Lin ,  Chun-Chi Chen

IPC: G01R33/09 ,  G11C11/16 ,  H01L27/22 ,  H01L43/12

Abstract: Disclosed methods include placing a semiconductor wafer containing MRAM devices into a first magnetic field that has a magnitude sufficient to magnetically polarize MRAM bits and has a substantially uniform field strength and direction over the entire area of the wafer. The method further includes placing the wafer in a second magnetic field having an opposite field direction, a substantially uniform field strength and direction over the entire area of the wafer, and magnitude less than a design threshold for MRAM bit magnetization reversal. The method further includes determining a presence of malfunctioning MRAM bits by determining that such malfunctioning MRAM bits have a magnetic polarization that was reversed due to exposure to the second magnetic field. Malfunctioning MRAM bits may further be characterized by electrically reading data bits, or by using a chip probe to read one or more of voltage, current, resistances, etc., of the MRAM devices.

公开(公告)号：US20240096818A1

公开(公告)日：2024-03-21

申请号：US18303659

申请日：2023-04-20

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Harry-Hak-Lay Chuang ,  Yuan-Jen Lee ,  Kuo-An Liu ,  Ching-Huang Wang ,  C.T. Kuo ,  Tien-Wei Chiang

IPC: H01L23/552 ,  H01L25/00 ,  H01L25/065 ,  H10B80/00

CPC classification number: H01L23/552 ,  H01L25/0655 ,  H01L25/50 ,  H10B80/00 ,  H10B61/00

Abstract: Devices and method for forming a shielding assembly including a first chip package structure sensitive to magnetic interference (MI), a second chip package structure sensitive to electromagnetic interference (EMI), and a shield surrounding sidewalls and top surfaces of the first chip package structure and the second chip package structure, in which the shield is a magnetic shielding material. In some embodiments, the shield may include silicon steel, in some embodiments, the shield may include Mu-metal. The silicon-steel-based or Mu-metal-based shield may provide both EMI and MI protection to multiple chip package structures with various susceptibilities to EMI and MI.