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7 条记录 (耗时 0.019 秒)

    Synchronous semiconductor memory device capable of selecting column at high speed
    1.
    发明授权
    Synchronous semiconductor memory device capable of selecting column at high speed 失效
    能够高速选择色谱柱的同步半导体存储器件

    公开(公告)号：US06243320B1

    公开(公告)日：2001-06-05

    申请号：US09265856

    申请日：1999-03-11

    申请人： Takeshi Hamamoto ,  Zenya Kawaguchi ,  Motoko Hara

    发明人： Takeshi Hamamoto ,  Zenya Kawaguchi ,  Motoko Hara

    IPC分类号： G11C800

    CPC分类号： G11C7/1072 ,  G11C8/18

    摘要： A command decoder receives an externally supplied command independently of an internal clock signal, decodes the command, generates a column access mode instruction signal, and activates a column address activation signal when the internal clock signal rises. An internal column address signal generating circuit generates an internal column address signal from an externally supplied address signal according to the column address activation signal. Accordingly, the internal column address is generated at an advanced timing to enable a following column selecting operation to be started at a faster timing. A synchronous semiconductor memory device capable of performing the column selecting operation at a high speed is thus provided.

    摘要翻译： 命令解码器独立于内部时钟信号接收外部提供的命令，解码该命令，产生列存取模式指令信号，并且当内部时钟信号上升时激活列地址激活信号。 内部列地址信号发生电路根据列地址激活信号从外部提供的地址信号产生内部列地址信号。 因此，在高级定时产生内部列地址，以使得能够以更快的定时开始以下列选择操作。 因此提供了能够高速执行列选择操作的同步半导体存储器件。

    Synchronous semiconductor memory device capable of selecting column at high speed
    2.
    发明授权
    Synchronous semiconductor memory device capable of selecting column at high speed 失效

    公开(公告)号：US06333892B2

    公开(公告)日：2001-12-25

    申请号：US09725851

    申请日：2000-11-30

    申请人： Takeshi Hamamoto ,  Zenya Kawaguchi ,  Motoko Hara

    发明人： Takeshi Hamamoto ,  Zenya Kawaguchi ,  Motoko Hara

    IPC分类号： G11C800

    CPC分类号： G11C7/1072 ,  G11C8/18

    摘要： A command decoder receives an externally supplied command independently of an internal clock signal, decodes the command, generates a column access mode instruction signal, and activates a column address activation signal when the internal clock signal rises. An internal column address signal generating circuit generates an internal column address signal from an externally supplied address signal according to the column address activation signal. Accordingly, the internal column address is generated at an advanced timing to enable a following column selecting operation to be started at a faster timing. A synchronous semiconductor memory device capable of performing the column selecting operation at a high speed is thus provided.

    IC substrate and boosted voltage generation circuits
    3.
    发明授权
    IC substrate and boosted voltage generation circuits 失效
    IC基板和升压电压发生电路

    公开(公告)号：US5530640A

    公开(公告)日：1996-06-25

    申请号：US135514

    申请日：1993-10-13

    申请人： Motoko Hara ,  Takeshi Kajimoto

    发明人： Motoko Hara ,  Takeshi Kajimoto

    IPC分类号： G05F1/46 ,  G11C5/14 ,  H02M1/36 ,  H02M3/07 ,  H02M3/18

    CPC分类号： H02M1/36 ,  G05F1/465 ,  G11C5/145 ,  G11C5/146 ,  H02M3/07

    摘要： A voltage generation circuit has a charge pump circuit, a clamping circuit for clamping an output voltage of the charge pump circuit, and detecting means for detecting the output voltage of the charge pump circuit and supplying a control signal for boosting the output voltage to the charge pump circuit when the detected output voltage is lower than a reference voltage, wherein the detecting means includes a circuit for stopping supply of a control signal. This circuit stops supply of the control signal to the charge pump circuit when the clamping circuit is in operation.

    摘要翻译： 电压产生电路具有电荷泵电路，用于钳位电荷泵电路的输出电压的钳位电路，以及用于检测电荷泵电路的输出电压并提供用于将输出电压升压到电荷的控制信号的检测装置 当所检测的输出电压低于参考电压时，所述检测装置包括用于停止提供控制信号的电路。 当钳位电路运行时，该电路停止向电荷泵电路供应控制信号。

    Semiconductor memory device capable of operating with potentials of adjacent bit lines inverted during multi-bit test
    4.
    发明授权
    Semiconductor memory device capable of operating with potentials of adjacent bit lines inverted during multi-bit test 失效
    能够在多位测试期间反相的相邻位线的电位进行操作的半导体存储器件

    公开(公告)号：US5654924A

    公开(公告)日：1997-08-05

    申请号：US640639

    申请日：1996-05-01

    申请人： Tomio Suzuki ,  Motoko Hara ,  Shigeru Mori

    发明人： Tomio Suzuki ,  Motoko Hara ,  Shigeru Mori

    IPC分类号： G11C29/00 ,  G11C29/06 ,  G11C29/28 ,  G11C29/36 ,  G11C29/50 ,  G11C7/00

    CPC分类号： G11C29/50 ,  G11C29/28 ,  G11C29/36

    摘要： A semiconductor memory device is provided which can apply a voltage stress to every adjacent bit lines even when data is written using a data bit compression function in a burn-in test mode. More specifically, when data is written using the data bit compression function in the test mode, an input buffer circuit is brought to a state in which it receives a signal corresponding to a signal dq0 applied to a specific input/output terminal by a switch circuit controlled by a test mode specify signal TE in common. When an inversion designate signal INV is in an active state, a complementary signal corresponding to a signal obtained by inversion of signal dq0 by an inverting circuit is output to internal data buses IO0, ZIO0, and IO2, ZIO2. On the other hand, a complementary signal corresponding to signal dq0 is output to internal data buses IO1, ZIO1, and IO3, ZIO3.

    摘要翻译： 提供了一种半导体存储器件，即使在老化测试模式下使用数据位压缩功能写数据时，也可以向每个相邻位线施加电压应力。 更具体地，当在测试模式中使用数据位压缩功能写入数据时，输入缓冲器电路进入其中通过开关电路接收与施加到特定输入/输出端子的信号dq0相对应的信号的状态 由测试模式控制，共同指定信号TE。 当反转指示信号INV处于活动状态时，与通过反相电路的信号dq0的反相获得的信号相对应的互补信号被输出到内部数据总线IO0，ZIO0和IO2，ZIO2。 另一方面，对应于信号dq0的互补信号被输出到内部数据总线IO1，ZIO1和IO3，ZIO3。

    Ring oscillator and constant voltage generation circuit
    5.
    发明授权
    Ring oscillator and constant voltage generation circuit 失效
    环形振荡器和恒压发生电路

    公开(公告)号：US5446418A

    公开(公告)日：1995-08-29

    申请号：US147268

    申请日：1993-11-05

    申请人： Motoko Hara ,  Takeshi Kajimoto

    发明人： Motoko Hara ,  Takeshi Kajimoto

    IPC分类号： H03K3/354 ,  G11C11/407 ,  G11C11/408 ,  H03K3/03 ,  H03K3/353

    CPC分类号： H03K3/0315

    摘要： A ring oscillator according to the invention includes a plurality of inverters cascade-connected between an input node and an output node. Each inverter includes four transistors connected in series between a power supply node and a ground node. A first pair of transistors each have a channel sized to have an input capacitance for delaying the signal of a preceding stage inverter for a prescribed time period. A second pair of transistors are coupled to a current mirror circuit and limits current flowing through the first pair of transistors. Thus, power consumption for obtaining a signal in a prescribed cycle is reduced.

    摘要翻译： 根据本发明的环形振荡器包括级联连接在输入节点和输出节点之间的多个反相器。 每个逆变器包括串联在电源节点和接地节点之间的四个晶体管。 第一对晶体管每个具有通道，其尺寸设置成具有用于将前级反相器的信号延迟规定时间段的输入电容。 第二对晶体管耦合到电流镜电路并限制流过第一对晶体管的电流。 因此，减少了在规定的周期内获得信号的功耗。

    Semiconductor integrated circuit device having output buffer
    7.
    发明授权
    Semiconductor integrated circuit device having output buffer 失效
    具有输出缓冲器的半导体集成电路器件

    公开(公告)号：US6163177A

    公开(公告)日：2000-12-19

    申请号：US219781

    申请日：1998-12-23

    申请人： Motoko Hara ,  Hiroshi Akamatsu ,  Yutaka Ikeda

    发明人： Motoko Hara ,  Hiroshi Akamatsu ,  Yutaka Ikeda

    IPC分类号： G11C11/417 ,  G11C11/407 ,  G11C11/409 ,  H03K19/017 ,  H03K19/0175 ,  H03B1/00 ,  H03K3/00

    CPC分类号： H03K19/01721

    摘要： An output buffer includes an NAND circuit, a first N channel MOS transistor connected between a power supply node and an output node, a second N channel MOS transistor connected between the output node and a ground node, the first to third drive circuits, and a delay circuit. The power supply voltage is first supplied to the gate of the second N channel MOS transistor by the second drive circuit. After a delay time delayed by the delay circuit has passed, boosted voltage is supplied to the gate of the second N channel MOS transistor by the third drive circuit. Accordingly, the output buffer is not influenced by the ringing and the pull-down characteristic improves.

    摘要翻译： 输出缓冲器包括NAND电路，连接在电源节点和输出节点之间的第一N沟道MOS晶体管，连接在输出节点和接地节点之间的第二N沟道MOS晶体管，第一至第三驱动电路和 延时电路。 电源电压首先通过第二驱动电路提供给第二N沟道MOS晶体管的栅极。 在延迟电路延迟的延迟时间过去之后，由第三驱动电路向第二N沟道MOS晶体管的栅极提供升压电压。 因此，输出缓冲器不受振铃影响，并且下拉特性提高。