公开(公告)号：US20060131271A1

公开(公告)日：2006-06-22

申请号：US11022983

申请日：2004-12-22

申请人： Adrian Kiermasz ,  Tamarak Pandhumsoporn ,  Alferd Cofer

发明人： Adrian Kiermasz ,  Tamarak Pandhumsoporn ,  Alferd Cofer

IPC分类号： C23F1/00

CPC分类号： C03C23/006 ,  C23C4/02 ,  H01J37/32935 ,  H01L21/67253

摘要： In a plasma processing system, a method for optimizing etching of a substrate is disclosed. The method includes selecting a first plasma process recipe including a first process variable, wherein changing the first process variable by a first amount optimizes a first substrate etch characteristic and aggravates a second substrate etch characteristic. The method also includes selecting second plasma process recipe including a second process variable, wherein changing the second process variable by a second amount aggravates the first substrate etch characteristic and optimizes the second substrate etch characteristic. The method further includes positioning a substrate on a chuck in a plasma processing chamber; and striking a plasma within the plasma processing chamber. The method also includes alternating between the first plasma recipe and the second plasma recipe, wherein upon completion of the alternating, the first substrate etch characteristic and the second substrate etch characteristic are substantially optimized.

摘要翻译： 在等离子体处理系统中，公开了一种用于优化衬底蚀刻的方法。 该方法包括选择包括第一过程变量的第一等离子体处理配方，其中以第一量改变第一过程变量优化第一衬底蚀刻特性并加重第二衬底蚀刻特性。 该方法还包括选择包括第二过程变量的第二等离子体处理配方，其中以第二量改变第二过程变量加剧了第一衬底蚀刻特性并优化了第二衬底蚀刻特性。 该方法还包括将基板定位在等离子体处理室中的卡盘上; 并在等离子体处理室内击打等离子体。 该方法还包括在第一等离子体配方和第二等离子体配方之间交替，其中在完成交替时，基本上优化了第一衬底蚀刻特性和第二衬底蚀刻特性。

公开(公告)号：US20070281489A1

公开(公告)日：2007-12-06

申请号：US11421000

申请日：2006-05-30

申请人： Tamarak Pandhumsoporn ,  Alferd Cofer ,  William Bosch

发明人： Tamarak Pandhumsoporn ,  Alferd Cofer ,  William Bosch

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/30655 ,  B81C1/00571 ,  H01L21/32137

摘要： A method for etching silicon layer of a substrate, which is deposited on a bottom electrode in a plasma processing chamber. The method includes performing a main etch step until at least 70 percent of silicon layer is etched. The method further includes an overetch step, which includes a first, second, and third process steps. The first process step employs a first process recipe, the second process step employs a second process recipe, and the third process step employs a third process recipe. The second process recipe employs a second bottom bias voltage level applied to the bottom electrode which is higher than the first bottom bias voltage level employs in the first process recipe and the third bottom bias voltage level employs in the third process recipe. The first, second, and third process steps are alternated a plurality of times until silicon layer is etched through.

摘要翻译： 一种用于蚀刻沉积在等离子体处理室中的底部电极上的衬底的硅层的方法。 该方法包括执行主蚀刻步骤，直到至少70％的硅层被蚀刻。 该方法还包括一个过程延伸步骤，其包括第一，第二和第三工艺步骤。 第一处理步骤采用第一处理配方，第二处理步骤采用第二处理配方，并且第三处理步骤采用第三处理配方。 第二工艺配方采用施加到底部电极的第二底部偏置电压电平，该第二底部偏置电压电平高于第一工艺配方中使用的第一底部偏置电压电平，而第三工艺配方中采用第三底部偏置电压电平。 第一，第二和第三工艺步骤交替多次，直到硅层被蚀刻通过。

公开(公告)号：US20070141847A1

公开(公告)日：2007-06-21

申请号：US11305440

申请日：2005-12-16

申请人： Tamarak Pandhumsoporn ,  Alferd Cofer

发明人： Tamarak Pandhumsoporn ,  Alferd Cofer

IPC分类号： C03C25/68 ,  H01L21/461 ,  H01L21/302 ,  C03C15/00

CPC分类号： H01L21/30655

摘要： A method for etching a substrate having a silicon layer in a plasma processing chamber having a bottom electrode on which the substrate is disposed on during etching. The method includes performing a main etch step. The method also includes terminating main etch step when a predefined etch depth of at least 70 percent of thickness into silicon layer is achieved. The method further includes performing an overetch step. The overetch step including a first process step and a second process step. First process step is performed using a first bottom power level applied to bottom electrode. Second process step is performed using a second bottom power level applied to bottom electrode that is lower than first bottom power level. First process and second process steps are alternately performed a plurality of times. The method yet also includes terminating overetch step after silicon layer is etched through.

摘要翻译： 一种用于在蚀刻期间蚀刻具有底层电极的等离子体处理室中具有硅层的衬底的方法。 该方法包括执行主蚀刻步骤。 当达到至少70％的厚度的预定蚀刻深度达到硅层时，该方法还包括终止主蚀刻步骤。 所述方法还包括执行过程延展步骤。 该疏水步骤包括第一工艺步骤和第二工艺步骤。 使用施加到底部电极的第一底部功率电平来执行第一处理步骤。 使用低于第一底部功率电平的施加到底部电极的第二底部功率电平来执行第二工艺步骤。 交替执行第一处理和第二处理步骤多次。 该方法还包括在蚀刻硅层之后终止过蚀刻步骤。

公开(公告)号：US07351664B2

公开(公告)日：2008-04-01

申请号：US11421000

申请日：2006-05-30

申请人： Tamarak Pandhumsoporn ,  Alferd Cofer ,  William Bosch

发明人： Tamarak Pandhumsoporn ,  Alferd Cofer ,  William Bosch

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/30655 ,  B81C1/00571 ,  H01L21/32137

摘要： A method for etching silicon layer of a substrate, which is deposited on a bottom electrode in a plasma processing chamber. The method includes performing a main etch step until at least 70 percent of silicon layer is etched. The method further includes an overetch step, which includes a first, second, and third process steps. The first process step employs a first process recipe, the second process step employs a second process recipe, and the third process step employs a third process recipe. The second process recipe employs a second bottom bias voltage level applied to the bottom electrode which is higher than the first bottom bias voltage level employs in the first process recipe and the third bottom bias voltage level employs in the third process recipe. The first, second, and third process steps are alternated a plurality of times until silicon layer is etched through.

摘要翻译： 一种用于蚀刻沉积在等离子体处理室中的底部电极上的衬底的硅层的方法。 该方法包括执行主蚀刻步骤，直到至少70％的硅层被蚀刻。 该方法还包括一个过程延伸步骤，其包括第一，第二和第三工艺步骤。 第一处理步骤采用第一处理配方，第二处理步骤采用第二处理配方，并且第三处理步骤采用第三处理配方。 第二工艺配方采用施加到底部电极的第二底部偏置电压电平，该第二底部偏置电压电平高于第一工艺配方中使用的第一底部偏置电压电平，而第三工艺配方中采用第三底部偏置电压电平。 第一，第二和第三工艺步骤交替多次，直到硅层被蚀刻通过。

公开(公告)号：US07985688B2

公开(公告)日：2011-07-26

申请号：US11305440

申请日：2005-12-16

申请人： Tamarak Pandhumsoporn ,  Alferd Cofer

发明人： Tamarak Pandhumsoporn ,  Alferd Cofer

IPC分类号： H01L21/302

CPC分类号： H01L21/30655

摘要： A method for etching a substrate having a silicon layer in a plasma processing chamber having a bottom electrode on which the substrate is disposed on during etching. The method includes performing a main etch step. The method also includes terminating main etch step when a predefined etch depth of at least 70 percent of thickness into silicon layer is achieved. The method further includes performing an overetch step. The overetch step including a first process step and a second process step. First process step is performed using a first bottom power level applied to bottom electrode. Second process step is performed using a second bottom power level applied to bottom electrode that is lower than first bottom power level. First process and second process steps are alternately performed a plurality of times. The method yet also includes terminating overetch step after silicon layer is etched through.

摘要翻译： 一种用于在蚀刻期间蚀刻具有底层电极的等离子体处理室中具有硅层的衬底的方法。 该方法包括执行主蚀刻步骤。 当达到至少70％的厚度的预定蚀刻深度达到硅层时，该方法还包括终止主蚀刻步骤。 所述方法还包括执行过程延展步骤。 该疏水步骤包括第一工艺步骤和第二工艺步骤。 使用施加到底部电极的第一底部功率电平来执行第一处理步骤。 使用低于第一底部功率电平的施加到底部电极的第二底部功率电平来执行第二工艺步骤。 交替执行第一处理和第二处理步骤多次。 该方法还包括在蚀刻硅层之后终止过蚀刻步骤。

公开(公告)号：US07459100B2

公开(公告)日：2008-12-02

申请号：US11022983

申请日：2004-12-22

申请人： Adrian Kiermasz ,  Tamarak Pandhumsoporn ,  Alferd Cofer

发明人： Adrian Kiermasz ,  Tamarak Pandhumsoporn ,  Alferd Cofer

IPC分类号： C23F1/00

CPC分类号： C03C23/006 ,  C23C4/02 ,  H01J37/32935 ,  H01L21/67253

摘要： In a plasma processing system, a method for optimizing etching of a substrate is disclosed. The method includes selecting a first plasma process recipe including a first process variable, wherein changing the first process variable by a first amount optimizes a first substrate etch characteristic and aggravates a second substrate etch characteristic. The method also includes selecting second plasma process recipe including a second process variable, wherein changing the second process variable by a second amount aggravates the first substrate etch characteristic and optimizes the second substrate etch characteristic. The method further includes positioning a substrate on a chuck in a plasma processing chamber; and striking a plasma within the plasma processing chamber. The method also includes alternating between the first plasma recipe and the second plasma recipe, wherein upon completion of the alternating, the first substrate etch characteristic and the second substrate etch characteristic are substantially optimized.

摘要翻译： 在等离子体处理系统中，公开了一种用于优化衬底蚀刻的方法。 该方法包括选择包括第一过程变量的第一等离子体处理配方，其中以第一量改变第一过程变量优化第一衬底蚀刻特性并加重第二衬底蚀刻特性。 该方法还包括选择包括第二过程变量的第二等离子体处理配方，其中以第二量改变第二过程变量加剧了第一衬底蚀刻特性并优化了第二衬底蚀刻特性。 该方法还包括将基板定位在等离子体处理室中的卡盘上; 并在等离子体处理室内击打等离子体。 该方法还包括在第一等离子体配方和第二等离子体配方之间交替，其中在完成交替时，基本上优化了第一衬底蚀刻特性和第二衬底蚀刻特性。

公开(公告)号：US20050164513A1

公开(公告)日：2005-07-28

申请号：US11087540

申请日：2005-03-23

申请人： Stephen DeOrnellas ,  Leslie Jerde ,  Alferd Cofer ,  Robert Vail ,  Kurt Olson

发明人： Stephen DeOrnellas ,  Leslie Jerde ,  Alferd Cofer ,  Robert Vail ,  Kurt Olson

IPC分类号： H05H1/46 ,  C23F4/00 ,  H01J37/32 ,  H01L21/02 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3213

CPC分类号： H01L21/02071 ,  H01J37/32082 ,  H01J37/32165 ,  H01J37/32587 ,  H01J37/32623 ,  H01J2237/334 ,  H01L21/3065 ,  H01L21/32136 ,  H01L28/55 ,  H01L28/60

摘要： A plasma etch reactor 20 includes a upper electrode 24, a lower electrode 24, a peripheral ring electrode 26 disposed therebetween. The upper electrode 24 is grounded, the peripheral electrode 26 is powered by a high frequency AC power supply, while the lower electrode 28 is powered by a low frequency AC power supply, as well as a DC power supply. The reactor chamber 22 is configured with a solid source 50 of gaseous species and a protruding baffle 40. A nozzle 36 provides a jet stream of process gases in order to ensure uniformity of the process gases at the surface of a semiconductor wafer 48. The configuration of the plasma etch reactor 20 enhances the range of densities for the plasma in the reactor 20, which range can be selected by adjusting more of the power supplies 30, 32.

摘要翻译： 等离子体蚀刻反应器20包括上电极24，下电极24，设置在其间的外围环电极26。 上电极24接地，外围电极26由高频交流电源供电，而下电极28由低频交流电源供电以及直流电源。 反应器室22配置有气态物质的固体源50和突出的挡板40。 喷嘴36提供工艺气体的喷射流，以确保半导体晶片48表面处理气体的均匀性。 等离子体蚀刻反应器20的配置增强了反应器20中的等离子体的密度范围，该范围可以通过调节更多的电源30,32来选择。

公开(公告)号：US6127277A

公开(公告)日：2000-10-03

申请号：US742861

申请日：1996-11-01

申请人： Stephen P. DeOrnellas ,  Alferd Cofer ,  Paritosh Rajora

发明人： Stephen P. DeOrnellas ,  Alferd Cofer ,  Paritosh Rajora

IPC分类号： H01L21/02 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/302

CPC分类号： H01L21/02071 ,  H01J37/32165 ,  H01J37/32587 ,  H01L21/3065 ,  H01L21/32136 ,  H01J2237/334

摘要： A method and apparatus provide for etching a semiconductor wafer using a two step physical etching and a chemical etching process in order to create vertical sidewalls required for high density DRAMs and FRAMs.

公开(公告)号：US06905969B2

公开(公告)日：2005-06-14

申请号：US10156478

申请日：2002-05-28

申请人： Stephen P. DeOrnellas ,  Leslie G. Jerde ,  Alferd Cofer ,  Robert C. Vail ,  Kurt A. Olson

发明人： Stephen P. DeOrnellas ,  Leslie G. Jerde ,  Alferd Cofer ,  Robert C. Vail ,  Kurt A. Olson

IPC分类号： H05H1/46 ,  C23F4/00 ,  H01J37/32 ,  H01L21/02 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3213

CPC分类号： H01L21/02071 ,  H01J37/32082 ,  H01J37/32165 ,  H01J37/32587 ,  H01J37/32623 ,  H01J2237/334 ,  H01L21/3065 ,  H01L21/32136 ,  H01L28/55 ,  H01L28/60

摘要： A plasma etch reactor 20 includes a upper electrode 24, a lower electrode 24, a peripheral ring electrode 26 disposed therebetween. The upper electrode 24 is grounded, the peripheral electrode 26 is powered by a high frequency AC power supply, while the lower electrode 28 is powered by a low frequency AC power supply, as well as a DC power supply. The reactor chamber 22 is configured with a solid source 50 of gaseous species and a protruding baffle 40. A nozzle 36 provides a jet stream of process gases in order to ensure uniformity of the process gases at the surface of a semiconductor wafer 48. The configuration of the plasma etch reactor 20 enhances the range of densities for the plasma in the reactor 20, which range can be selected by adjusting more of the power supplies 30, 32.

公开(公告)号：US06492280B1

公开(公告)日：2002-12-10

申请号：US09517387

申请日：2000-03-02

申请人： Stephen P. DeOrnellas ,  Alferd Cofer ,  Paritosh Rajora

发明人： Stephen P. DeOrnellas ,  Alferd Cofer ,  Paritosh Rajora

IPC分类号： H01L21302

CPC分类号： H01L21/02071 ,  H01J37/32082 ,  H01J37/32165 ,  H01J37/32587 ,  H01J2237/334 ,  H01L21/3065 ,  H01L21/32136 ,  H01L28/55 ,  H01L28/60

摘要： A method and apparatus provide for etching a semiconductor wafer using a two step physical etching and a chemical etching process in order to create vertical sidewalls required for high density DRAMs and FRAMs.

摘要翻译： 一种方法和装置提供了使用两步物理蚀刻和化学蚀刻工艺来蚀刻半导体晶片，以便产生高密度DRAM和FRAM所需的垂直侧壁。