-
1.发明授权Method and apparatus for etching a semiconductor wafer with features having vertical sidewalls 失效用于蚀刻具有垂直侧壁的特征的半导体晶片的方法和设备公开(公告)号：US06492280B1
公开(公告)日：2002-12-10
申请号：US09517387
申请日：2000-03-02
Applicant: Stephen P. DeOrnellas , Alferd Cofer , Paritosh Rajora
Inventor： Stephen P. DeOrnellas , Alferd Cofer , Paritosh Rajora
IPC: H01L21302
CPC classification number: H01L21/02071 , H01J37/32082 , H01J37/32165 , H01J37/32587 , H01J2237/334 , H01L21/3065 , H01L21/32136 , H01L28/55 , H01L28/60
Abstract: A method and apparatus provide for etching a semiconductor wafer using a two step physical etching and a chemical etching process in order to create vertical sidewalls required for high density DRAMs and FRAMs.
Abstract translation: 一种方法和装置提供了使用两步物理蚀刻和化学蚀刻工艺来蚀刻半导体晶片，以便产生高密度DRAM和FRAM所需的垂直侧壁。
-
Patent Agency Ranking
公开(公告)号：US20130001188A1
公开(公告)日：2013-01-03
申请号：US13174321
申请日：2011-06-30
Applicant: David Kuo , Michael R. Feldbaum , Paritosh Rajora , Hieu Lam
Inventor： David Kuo , Michael R. Feldbaum , Paritosh Rajora , Hieu Lam
CPC classification number: H01L43/12 , Y10T428/24628
Abstract: The embodiments disclose a method to protect magnetic bits during carbon field planarization, including depositing a stop layer upon magnetic bits and magnetic film of a patterned stack, depositing a carbon fill layer on the stop layer and using the stop layer during planarization and etch-back of the carbon field to protect the patterned stack magnetic bits during the carbon field planarization.
Abstract translation: 这些实施例公开了一种在碳场平坦化期间保护磁头的方法，包括在图案化堆叠的磁头和磁性膜上沉积停止层，在停止层上沉积碳填充层并在平坦化和回蚀刻期间使用停止层 的碳场以在碳场平坦化期间保护图案化的堆叠磁性位。
-
3.发明授权
公开(公告)号：US6127277A
公开(公告)日：2000-10-03
申请号：US742861
申请日：1996-11-01
Applicant: Stephen P. DeOrnellas , Alferd Cofer , Paritosh Rajora
Inventor： Stephen P. DeOrnellas , Alferd Cofer , Paritosh Rajora
IPC: H01L21/02 , H01L21/3065 , H01L21/3213 , H01L21/302
CPC classification number: H01L21/02071 , H01J37/32165 , H01J37/32587 , H01L21/3065 , H01L21/32136 , H01J2237/334
Abstract: A method and apparatus provide for etching a semiconductor wafer using a two step physical etching and a chemical etching process in order to create vertical sidewalls required for high density DRAMs and FRAMs.
-
4.发明申请PATTERNING MAGNETIC RECORDING MEDIA WITH ION IMPLANTATION UTILIZING A COMBINATION OF HEAVY AND LIGHT ION SPECIES 审中-公开使用重型和轻质物质组合的离子植入来绘制磁记录介质公开(公告)号：US20100300874A1
公开(公告)日：2010-12-02
申请号：US12473510
申请日：2009-05-28
Applicant: David Shiao-Min Kuo , Dieter Weller , Jan-Ulrich Thiele , Justin Hwu , Paritosh Rajora
Inventor： David Shiao-Min Kuo , Dieter Weller , Jan-Ulrich Thiele , Justin Hwu , Paritosh Rajora
IPC: C23C14/46
Abstract: A patterned magnetic layer is formed by bombardment of a masked high Mrt magnetic layer with a combination of both heavy ion species and light ion species. The method can be implemented as sequential process steps or in a single process step with the proper heavy/light ion species mixture. Advantageously, the combined heavy/light ion species bombardment method results in a patterned magnetic layer having high topographical uniformity across its surface.
Abstract translation: 通过用重离子物质和轻离子物质的组合轰击掩蔽的高Mrt磁性层形成图案化的磁性层。 该方法可以作为顺序的工艺步骤或在具有适当的重/轻离子物质混合物的单一工艺步骤中实施。 有利地，组合的重/轻离子物质轰击方法导致在其表面上具有高形貌均匀性的图案化磁性层。
-
5.发明授权Method for minimizing the critical dimension growth of a feature on a semiconductor wafer 有权用于最小化半导体晶片上的特征的临界尺寸增长的方法公开(公告)号：US06774046B2
公开(公告)日：2004-08-10
申请号：US09880584
申请日：2001-06-13
Applicant: Stephen P. DeOrnellas , Alferd Cofer , Leslie G. Jerde , Kurt A. Olson , Paritosh Rajora
Inventor： Stephen P. DeOrnellas , Alferd Cofer , Leslie G. Jerde , Kurt A. Olson , Paritosh Rajora
IPC: H01I21302
CPC classification number: H01L21/3065 , H01L21/31116 , H01L21/32136
Abstract: A method for minimizing the critical dimension growth of a feature on a semiconductor wafer includes performing an etch operation in a reactor 20 and controlling the temperature of the wafer 26 by controlling the pressure of the gas contacting the backside of the wafer 26 and/or providing a heat source 56 such as for example in the chuck 46 or electrode 28 associated with the wafer 26 in order to heat the wafer 26.
Abstract translation: 用于最小化半导体晶片上的特征的临界尺寸增长的方法包括在反应器20中执行蚀刻操作并且通过控制接触晶片26的背侧的气体的压力和/或提供晶片26的背面来控制晶片26的温度 热源56，例如在与晶片26相关联的卡盘46或电极28中，以加热晶片26。
-
6.发明授权Method for minimizing the critical dimension growth of a feature on a semiconductor wafer 失效用于最小化半导体晶片上的特征的临界尺寸增长的方法
公开(公告)号：US6046116A
公开(公告)日：2000-04-04
申请号：US974089
申请日：1997-11-19
Applicant: Stephen P. DeOrnellas , Alfred Cofer , Leslie G. Jerde , Kurt A. Olson , Paritosh Rajora
Inventor： Stephen P. DeOrnellas , Alfred Cofer , Leslie G. Jerde , Kurt A. Olson , Paritosh Rajora
IPC: H01L21/302 , H01L21/3065 , H01L21/311 , H01L21/3213
CPC classification number: H01L21/3065 , H01L21/31116 , H01L21/32136
Abstract: A method for minimizing the critical dimension growth of a feature on a semiconductor wafer includes performing an etch operation in a reactor 20 and controlling the temperature of the wafer 26 by controlling the pressure of the gas contacting the backside of the wafer 26 and/or providing a heat source 56 such as for example in the chuck 46 or electrode 28 associated with the wafer 26 in order to heat the wafer 26.
Abstract translation: 用于最小化半导体晶片上的特征的临界尺寸增长的方法包括在反应器20中执行蚀刻操作并且通过控制接触晶片26的背侧的气体的压力和/或提供晶片26的背面来控制晶片26的温度 热源56，例如在与晶片26相关联的卡盘46或电极28中，以加热晶片26。
-
-
-
-
-
Search Results
6
records
(took 0.008 seconds)
