公开(公告)号：US06535154B1

公开(公告)日：2003-03-18

申请号：US10008486

申请日：2001-11-05

申请人： Terry L. Sculley

发明人： Terry L. Sculley

IPC分类号： H03M302

CPC分类号： H03M1/0668 ,  H03M1/74 ,  H03M3/464 ,  H03M3/502

摘要： Noise-shaped dynamic element matching in analog-to-digital and digital-to-analog converters is increased in such a way that the number of components increases linearly, rather than exponentially, as the number of bits is increased. A processor generates a plurality of input signals for a plurality of digital delta sigma modulators which, in turn, generate a plurality of control signals for selecting a plurality of weighted converter elements. The processor recursively generates the input signals in such a way that the control signals generated by some of the digital delta sigma modulators include error cancellation components to cancel error components in other control signals.

摘要翻译： 模数转换器和数模转换器中的噪声形状的动态元件匹配以这样的方式增加，即随着位数的增加，分量的数量线性增加而不是指数地增加。 处理器为多个数字Δ-Σ调制器产生多个输入信号，其又产生用于选择多个加权转换器元件的多个控制信号。 处理器以这样的方式递归地产生输入信号，使得由一些数字Δ-Σ调制器产生的控制信号包括消除其它控制信号中的误差分量的误差消除分量。

公开(公告)号：US06326818B1

公开(公告)日：2001-12-04

申请号：US09527554

申请日：2000-03-16

申请人： Terry L. Sculley

发明人： Terry L. Sculley

IPC分类号： G11C2702

CPC分类号： G11C27/026

摘要： A method and apparatus for performing voltage-mode sample and hold functions while avoiding nonlinear charge injection. The method comprises oversampling an input signal and sampling an error signal, not the input signal directly, and through signal processing causing the error signal to be reduced to low amplitude. First order and higher order voltage-mode sample and hold circuitry embodiments are provided.

摘要翻译： 一种用于在避免非线性电荷注入的同时执行电压模式采样和保持功能的方法和装置。 该方法包括对输入信号进行过采样，并对误差信号进行采样，而不是直接对输入信号进行采样，并通过使误差信号降低到低振幅的信号处理。 提供了一阶和高阶电压模式采样和保持电路实施例。

公开(公告)号：US20110054913A1

公开(公告)日：2011-03-03

申请号：US12553713

申请日：2009-09-03

申请人： Shawn X. Yu ,  Terry L. Sculley

发明人： Shawn X. Yu ,  Terry L. Sculley

IPC分类号： G10L11/00 ,  H04L27/06

CPC分类号： H04L25/0262 ,  G06F3/162 ,  G10L19/24 ,  H03H17/0628 ,  H04L25/05

摘要： In recent years, it has become commonplace for portable devices to generate analog audio signals from numerous sources, meaning that the codecs employed in these portable devices need to be able to utilize various digital bit streams at different sampling rates. To date, however, the circuitry for asynchronous sampling rate conversions for multiple bit streams has been complex, rigid, and power hungry. Here, a codec is provided which uses miniDSP cores to perform asynchronous sampling rate conversion efficiently and with reduced power consumption compared to other conventional codecs.

摘要翻译： 近年来，便携式设备从许多来源产生模拟音频信号已成为常见现象，这意味着在这些便携式设备中采用的编解码器需要能够以不同的采样率利用各种数字比特流。 然而，到目前为止，用于多个比特流的异步采样率转换的电路是复杂，刚性和电力饥饿的。 这里提供了一种编解码器，与其他常规编解码器相比，使用miniDSP内核有效地执行异步采样率转换并降低功耗。

公开(公告)号：US07733151B1

公开(公告)日：2010-06-08

申请号：US12316166

申请日：2008-12-08

申请人： Shawn Xianggang Yu ,  Terry L. Sculley

发明人： Shawn Xianggang Yu ,  Terry L. Sculley

IPC分类号： H03K3/00

CPC分类号： H03K5/1565 ,  G06F1/08 ,  H03L7/183

摘要： A clock signal generator (1) includes a phase locked loop (PLL) circuit (25) which requires a reference clock signal of at least a predetermined first frequency (fDIGCLK). A first clock signal (REFCLK) of a second frequency (fREF) that is substantially lower than the first frequency (fDIGCLK) is multiplied so as to produce a second clock signal (DIGCLK) which has a frequency at least as high as the first frequency (fDIGCLK) and which is phase-locked with respect to the first clock signal (REFCLK). The second clock signal (DIGCLK) is applied to a reference signal input of the PLL circuit (25), which produces an output clock signal (PLLCLK or CLKOUT).

摘要翻译： 时钟信号发生器（1）包括需要至少预定的第一频率（fDIGCLK）的参考时钟信号的锁相环（PLL）电路（25）。 将基本上低于第一频率（fDIGCLK）的第二频率（fREF）的第一时钟信号（REFCLK）相乘以便产生具有至少与第一频率一样高的频率的第二时钟信号（DIGCLK） （fDIGCLK），并且其相对于第一时钟信号（REFCLK）是相位锁定的。 第二时钟信号（DIGCLK）被施加到产生输出时钟信号（PLLCLK或CLKOUT）的PLL电路（25）的参考信号输入端。

公开(公告)号：US07479912B1

公开(公告)日：2009-01-20

申请号：US11900760

申请日：2007-09-13

申请人： Shawn Xianggang ,  Mark S. Toth ,  Terry L. Sculley

发明人： Shawn Xianggang ,  Mark S. Toth ,  Terry L. Sculley

IPC分类号： H03M1/66

CPC分类号： G06F3/05 ,  H04W52/0287 ,  Y02D70/122

摘要： A low-power data conversion system for converting a serial digital data input signal (DIN) to an analog output signal (Vout) by generating the serial digital data input signal (DIN) at a first sample rate (fsin) in a burst mode, wherein the sampling frequency of the serial digital data input signal (DIN) has a predetermined ratio to the frequency of an external reference clock signal (SLEEPCLK or WCLK). The serial digital data input signal (DIN) is converted into parallel format. A FIFO system temporarily stores a predetermined number of samples (Din) of the parallel format digital data input signal. The samples (Din) have a first sample rate (fsin). The samples (Din) are converted to an analog output signal (Vout).

摘要翻译： 一种低功率数据转换系统，用于通过在突发模式下以第一采样率（fsin）产生串行数字数据输入信号（DIN），将串行数字数据输入信号（DIN）转换为模拟输出信号（Vout） 其中串行数字数据输入信号（DIN）的采样频率与外部参考时钟信号（SLEEPCLK或WCLK）的频率具有预定比例。 串行数字数据输入信号（DIN）被转换为并行格式。 FIFO系统临时存储并行格式数字数据输入信号的预定数量的样本（Din）。 样品（Din）具有第一采样率（fsin）。 样本（Din）被转换为模拟输出信号（Vout）。

公开(公告)号：US07262716B2

公开(公告)日：2007-08-28

申请号：US10325202

申请日：2002-12-20

申请人： Xianggang Yu ,  Terry L. Sculley ,  Jung-Kuei Chang

发明人： Xianggang Yu ,  Terry L. Sculley ,  Jung-Kuei Chang

IPC分类号： H03M7/00

CPC分类号： H03H17/0628

摘要： An asynchronous sample rate converter interpolates and filters a digital audio input signal to produce a filtered, up-sampled first signal. A FIFO memory receives the first signal and stores samples thereof at locations determined by a write address and presents stored samples from locations determined by a read address. The presented samples are passed through an interpolation and resampling circuit to produce a continuous-time signal which is re-sampled to produce a signal that is up-sampled relative to a desired output. That signal then is filtered and down-sampled to produce the output signal. Sample rate estimating circuitry computes a difference signal representative of a time at which a data sample of the audio input signal is received and a time at which a corresponding audio output sample is required, and address generation circuitry generates the read and write addresses. A coefficient calculation circuit calculates filter coefficients for the interpolation and resampling circuit in response to the difference signal.

摘要翻译： 异步采样率转换器对数字音频输入信号进行内插和滤波，以产生经过滤波的上采样的第一信号。 FIFO存储器接收第一信号并将其样本存储在由写地址确定的位置处，并且从由读地址确定的位置呈现存储的样本。 所呈现的样本通过内插和重采样电路以产生连续时间信号，该连续时间信号被重新采样以产生相对于期望输出被上采样的信号。 然后对该信号进行滤波和下采样以产生输出信号。 采样率估计电路计算表示接收音频输入信号的数据采样的时间和需要相应音频输出采样的时间的差信号，地址产生电路产生读和写地址。 系数计算电路响应于差分信号来计算内插和重采样电路的滤波器系数。

公开(公告)号：US07408485B1

公开(公告)日：2008-08-05

申请号：US11726414

申请日：2007-03-22

申请人： Shawn Xianggang Yu ,  Terry L. Sculley

发明人： Shawn Xianggang Yu ,  Terry L. Sculley

IPC分类号： H03M7/00

CPC分类号： H03H17/0614 ,  H03H17/0628

摘要： A sample rate converter suitable for use in an audio DAC includes a first estimating circuit (32A) generating first (TR) and second (STAMPR) signals synchronized to an asynchronous clock (MCLK) and representing the period and edge arrival times, respectively, of a reference clock (REFCLK). A second estimating circuit (32B) operates on the first and second signals to generate third (T1) and fourth (STAMP1) signals representing an input sample rate (32fsin) and arrival times of input data samples, respectively, which are applied to a coefficient and address generator (76) to generate read addresses and coefficients input to a FIFO memory (42) receiving digital input data at the input sample rate and a multiplication/accumulation circuit (78) receiving data from the FIFO memory. The multiplication/accumulation circuit produces an output signal (SRC-out) synchronized to the asynchronous clock at an output sample rate (32fsout).

摘要翻译： 适用于音频DAC的采样率转换器包括分别产生与异步时钟（MCLK）同步并分别表示周期和边缘到达时间的第一（TR）和第二（STAMPR）信号的第一估计电路（32A） 的参考时钟（REFCLK）。 第二估计电路（32B）对第一和第二信号进行操作以分别产生表示输入采样率（32fsin）和输入数据采样到达时间的第三（T 1）和第四（STAMP 1）信号 到系数和地址发生器（76），以产生输入到以输入采样率接收数字输入数据的FIFO存储器（42）的读地址和系数;以及从FIFO存储器接收数据的乘法/累加电路（78）。 乘法/累积电路以输出采样率（32fsout）产生与异步时钟同步的输出信号（SRC-out）。

公开(公告)号：US06747858B1

公开(公告)日：2004-06-08

申请号：US10335085

申请日：2002-12-31

申请人： Terry L. Sculley ,  Xianggang Yu

发明人： Terry L. Sculley ,  Xianggang Yu

IPC分类号： H03M700

CPC分类号： H03H17/0621 ,  H03H17/0223

摘要： A digital sample rate converter converts a digital input signal (Din) having a first sample rate (Fs_in) to a corresponding digital output signal Dout having a second sample rate (Fs_out), wherein an upsampling circuit (3) upsamples the digital input signal (Din) by a factor of N and a feedback algorithm circuit (23A) receives a corresponding digital signal of the same sample rate (Fs_in*N) to produce a digital signal (X6) having a sample rate which is a second predetermined factor (M) times the second sample rate (Fs_out). That signal is filtered by a decimation filter (17) and then downsampled by a predetermined factor to produce the digital output signal (Dout) with the second sample rate (Fs_out).

摘要翻译： 数字采样率转换器将具有第一采样率（Fs_in）的数字输入信号（Din）转换为具有第二采样率（Fs_out）的对应数字输出信号Dout，其中上采样电路（3）对数字输入信号 Din），并且反馈算法电路（23A）接收相同采样率（Fs_in * N）的相应数字信号，以产生具有作为第二预定因子（M）的采样率的数字信号（X6） ）乘以第二采样率（Fs_out）。 该信号由抽取滤波器（17）滤波，然后用预定因子进行下采样，以产生具有第二采样率（Fs_out）的数字输出信号（Dout）。

公开(公告)号：US08438036B2

公开(公告)日：2013-05-07

申请号：US12553713

申请日：2009-09-03

申请人： Shawn X. Yu ,  Terry L. Sculley

发明人： Shawn X. Yu ,  Terry L. Sculley

IPC分类号： G10L19/00

CPC分类号： H04L25/0262 ,  G06F3/162 ,  G10L19/24 ,  H03H17/0628 ,  H04L25/05

摘要： In recent years, it has become commonplace for portable devices to generate analog audio signals from numerous sources, meaning that the codecs employed in these portable devices need to be able to utilize various digital bit streams at different sampling rates. To date, however, the circuitry for asynchronous sampling rate conversions for multiple bit streams has been complex, rigid, and power hungry. Here, a codec is provided which uses miniDSP cores to perform asynchronous sampling rate conversion efficiently and with reduced power consumption compared to other conventional codecs.

摘要翻译： 近年来，便携式设备从许多来源产生模拟音频信号已成为常见现象，这意味着在这些便携式设备中采用的编解码器需要能够以不同的采样率利用各种数字比特流。 然而，到目前为止，用于多个比特流的异步采样率转换的电路是复杂，刚性和电力饥饿的。 这里提供了一种编解码器，与其他常规编解码器相比，使用miniDSP内核有效地执行异步采样率转换并降低功耗。

公开(公告)号：US20100141310A1

公开(公告)日：2010-06-10

申请号：US12316166

申请日：2008-12-08

申请人： Shawn Xianggang Yu ,  Terry L. Sculley

发明人： Shawn Xianggang Yu ,  Terry L. Sculley

IPC分类号： H03L7/06

CPC分类号： H03K5/1565 ,  G06F1/08 ,  H03L7/183

摘要： A clock signal generator (1) includes a phase locked loop (PLL) circuit (25) which requires a reference clock signal of at least a predetermined first frequency (fDIGCLK). A first clock signal (REFCLK) of a second frequency (fREF) that is substantially lower than the first frequency (fDIGCLK) is multiplied so as to produce a second clock signal (DIGCLK) which has a frequency at least as high as the first frequency (fDIGCLK) and which is phase-locked with respect to the first clock signal (REFCLK). The second clock signal (DIGCLK) is applied to a reference signal input of the PLL circuit (25), which produces an output clock signal (PLLCLK or CLKOUT).

摘要翻译： 时钟信号发生器（1）包括需要至少预定的第一频率（fDIGCLK）的参考时钟信号的锁相环（PLL）电路（25）。 将基本上低于第一频率（fDIGCLK）的第二频率（fREF）的第一时钟信号（REFCLK）相乘以便产生具有至少与第一频率一样高的频率的第二时钟信号（DIGCLK） （fDIGCLK），并且其相对于第一时钟信号（REFCLK）是相位锁定的。 第二时钟信号（DIGCLK）被施加到产生输出时钟信号（PLLCLK或CLKOUT）的PLL电路（25）的参考信号输入端。