公开(公告)号：US20250031445A1

公开(公告)日：2025-01-23

申请号：US18905538

申请日：2024-10-03

Applicant: Texas Instruments Incorporated

Inventor： Pushpa Mahalingam ,  Alexei Sadovnikov

IPC: H01L27/092 ,  H01L21/265 ,  H01L21/266 ,  H01L21/8238

Abstract: A microelectronic device including an analog MOS transistor. The analog transistor has a body well having a first conductivity type in a semiconductor material of a substrate of the microelectronic device. The body well extends deeper in the substrate than a field relief dielectric layer at the top surface of the semiconductor material. The analog transistor has a drain well and a source well having a second, opposite, conductivity type in the semiconductor material, both contacting the body well. The drain well and the source well extend deeper in the substrate than the field relief dielectric layer. The analog transistor has a gate on a gate dielectric layer over the body well. The drain well and the source well extend partway under the gate at the top surface of the semiconductor material.

公开(公告)号：US20240038580A1

公开(公告)日：2024-02-01

申请号：US17877976

申请日：2022-07-31

Applicant: Texas Instruments Incorporated

Inventor： Hao Yang ,  Asad Haider ,  Guruvayurappan Mathur ,  Abbas Ali ,  Alexei Sadovnikov ,  Umamaheswari Aghoram

IPC: H01L21/762 ,  H01L29/06

CPC classification number: H01L21/76229 ,  H01L29/0623

Abstract: An electronic device includes a semiconductor substrate and a semiconductor surface layer having a first conductivity type, the semiconductor surface layer over the semiconductor substrate and having a top surface, a buried layer having an opposite second conductivity type between the semiconductor surface layer and the semiconductor substrate, a dielectric isolation layer that extends over and into the semiconductor surface layer, a deep trench structure that extends through the dielectric isolation layer into the semiconductor surface layer, and a silicide blocking layer on a top surface of the deep trench structure.

公开(公告)号：US20230411452A1

公开(公告)日：2023-12-21

申请号：US17829009

申请日：2022-05-31

Applicant: Texas Instruments Incorporated

Inventor： Sheldon Douglas Haynie ,  Alexei Sadovnikov ,  Brian Goodlin

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0657 ,  H01L29/66795 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7853

Abstract: A method forms a semiconductor device with a substrate including semiconductor material formed to include plural corrugation members, each member including a top surface, and a first and second sidewall extending from the top surface to a lower surface. The method forms a contiguous transistor source extending through a first volume of each of the corrugation members and a first lower surface volume and a contiguous transistor drain extending through a second volume of each of the corrugation members and a second lower surface volume. Both source and drain are formed by initially diffusing a dopant in a uniform manner normal to various portions, some non-coplanar, of the source and drain, respectively.

公开(公告)号：US20230317846A1

公开(公告)日：2023-10-05

申请号：US17710773

申请日：2022-03-31

Applicant: Texas Instruments Incorporated

Inventor： Clint Alan Naquin ,  Henry Litzmann Edwards ,  Alexei Sadovnikov

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7823 ,  H01L29/0653 ,  H01L29/66689

Abstract: A microelectronic device including a substrate having a semiconductor material containing a laterally diffused metal oxide semiconductor (LDMOS) transistor, including a body region of a first conductivity type and a drift region of an opposite conductivity type. A gate dielectric layer over a channel region of the body, the gate dielectric extending over a junction between a body region and the drift region with a gate electrode on the gate dielectric and a drain contact in the drain drift region, having the second conductivity type. A field relief dielectric layer on the drain drift region extending from the drain region to the gate dielectric, having a thickness greater than the gate dielectric layer. A silicide-blocking layer extends from the drain region toward the gate, providing an unsilicided portion of the drift region at the substrate top surface between the drain region and the gate.

公开(公告)号：US11195958B2

公开(公告)日：2021-12-07

申请号：US17023639

申请日：2020-09-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Binghua Hu ,  Alexei Sadovnikov ,  Abbas Ali ,  Yanbiao Pan ,  Stefan Herzer

IPC: H01L29/66 ,  H01L29/94 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423

Abstract: A semiconductor device with an isolation structure and a trench capacitor, each formed using a single resist mask for etching corresponding first and second trenches of different widths and different depths, with dielectric liners formed on the trench sidewalls and polysilicon filling the trenches and deep doped regions surrounding the trenches, including conductive features of a metallization structure that connect the polysilicon of the isolation structure trench to the deep doped region to form an isolation structure.

公开(公告)号：US10978559B1

公开(公告)日：2021-04-13

申请号：US16983585

申请日：2020-08-03

Applicant: Texas Instruments Incorporated

Inventor： Sheldon Douglas Haynie ,  Alexei Sadovnikov

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40

Abstract: A semiconductor device includes a folded drain extended metal oxide semiconductor (DEMOS) transistor. The semiconductor device has a substrate including a semiconductor material with a corrugated top surface. The corrugated top surface has an upper portion, a lower portion, a first lateral portion extending from the upper portion to the lower portion, and a second lateral portion extending from the upper portion to the lower portion. The folded DEMOS transistor includes a body in the semiconductor material, a gate on a gate dielectric layer over the body, a drift region contacting the body, and a field plate on a field plate dielectric layer, all extending continuously along the upper portion, the first lateral portion, the second lateral portion, and the lower portion of the corrugated top surface. Methods of forming the folded DEMOS transistor are disclosed.

公开(公告)号：US10580775B2

公开(公告)日：2020-03-03

申请号：US15681466

申请日：2017-08-21

Applicant: Texas Instruments Incorporated

Inventor： Sameer Pendharkar ,  Binghua Hu ,  Alexei Sadovnikov ,  Guru Mathur

IPC: H01L21/762 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/765

Abstract: A semiconductor device adopts an isolation scheme to protect low voltage transistors from high voltage operations. The semiconductor device includes a substrate, a buried layer, a transistor well region, a first trench, and a second trench. The substrate has a top surface and a bottom surface. The buried layer is positioned within the substrate, and the transistor well region is positioned above the buried layer. The first trench extends from the top surface to penetrate the buried layer, and the first trench has a first trench depth. The second trench extending from the top surface to penetrate the buried layer. The second trench is interposed between the first trench and the transistor well region. The second trench has a second trench depth that is less than the first trench depth.

公开(公告)号：US09831135B2

公开(公告)日：2017-11-28

申请号：US15420296

申请日：2017-01-31

Applicant: Texas Instruments Incorporated

Inventor： Natalia Lavrovskaya ,  Alexei Sadovnikov ,  Andrew D. Strachan

IPC: H01L21/337 ,  H01L21/8249 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/08 ,  H01L27/06 ,  H01L29/866 ,  H01L29/06 ,  H01L29/732

CPC classification number: H01L21/8249 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0623 ,  H01L27/0635 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66106 ,  H01L29/66234 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/866

Abstract: The betas of the bipolar transistors in a BiCMOS semiconductor structure are increased by forming the emitters of the bipolar transistors with two implants: a source-drain implant that forms a first emitter region at the same time that the source and drain regions are formed, and an additional implant that forms a second emitter region at the same time that another region is formed. The additional implant has an implant energy that is greater than the implant energy of the source-drain implant.

公开(公告)号：US20170140991A1

公开(公告)日：2017-05-18

申请号：US15420296

申请日：2017-01-31

Applicant: Texas Instruments Incorporated

Inventor： Natalia Lavrovskaya ,  Alexei Sadovnikov ,  Andrew D. Strachan

IPC: H01L21/8249 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L21/8238 ,  H01L27/06

CPC classification number: H01L21/8249 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0623 ,  H01L27/0635 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66106 ,  H01L29/66234 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/866

Abstract: The betas of the bipolar transistors in a BiCMOS semiconductor structure are increased by forming the emitters of the bipolar transistors with two implants: a source-drain implant that forms a first emitter region at the same time that the source and drain regions are formed, and an additional implant that forms a second emitter region at the same time that another region is formed. The additional implant has an implant energy that is greater than the implant energy of the source-drain implant.

公开(公告)号：US20150340448A1

公开(公告)日：2015-11-26

申请号：US14286805

申请日：2014-05-23

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey A. Babcock ,  Alexei Sadovnikov

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/0623 ,  H01L21/32139 ,  H01L21/8249 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/402 ,  H01L29/423 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/66553 ,  H01L29/66575 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/66712 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7824 ,  H01L29/7835

Abstract: A method of fabricating a MOSFET transistor in a SiGe BICMOS technology and resulting structure having a drain-gate feedback capacitance shield formed between a gate electrode and the drain region. The shield does not overlap the gate and thereby minimizes effect on the input capacitance of the transistor. The process does not require complex or costly processing since the shield is composed of bipolar base material commonly used in SiGe BICMOS technologies.

Abstract translation: 一种以SiGe BICMOS技术制造MOSFET晶体管的方法，其结构在栅电极和漏极区之间形成漏极 - 栅极反馈电容屏蔽。 屏蔽不与栅极重叠，从而最小化对晶体管的输入电容的影响。 该过程不需要复杂或昂贵的处理，因为屏蔽由SiGe BICMOS技术中通常使用的双极母材组成。