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公开(公告)号：US20250155327A1
公开(公告)日：2025-05-15
申请号：US18508889
申请日：2023-11-14
Applicant: Texas Instruments Incorporated
Inventor： Anand Kumar G , Veeramanikandan Raju
IPC: G01M99/00
Abstract: An example apparatus includes: interface circuitry; and diagnostic circuitry configured to: determine a set of signal chains that may be used by an application, a signal chain in the set to include an ordered sequence of one or more circuit modules; identify a first signal chain from the set that was used by the application; and run, in response to a determination that the circuit modules in the first signal chain are idle, a diagnostic test on the first signal chain.
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公开(公告)号：US20250111096A1
公开(公告)日：2025-04-03
申请号：US18375732
申请日：2023-10-02
Applicant: Texas Instruments Incorporated
Inventor： Veeramanikandan Raju , Anand Kumar G
IPC: G06F21/75
Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to protect against voltage glitch attacks in microcontrollers. An example apparatus includes logic circuitry operable to, in response to a voltage glitch, pause processing circuitry; number generator circuitry operable to generate a number; a counter operable to, after the voltage glitch ends, adjust a count corresponding to the number; and the logic circuitry operable to unpause the processing circuitry after the count reaches a value.
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公开(公告)号：US20250035492A1
公开(公告)日：2025-01-30
申请号：US18918466
申请日：2024-10-17
Applicant: Texas Instruments Incorporated
Inventor： Anand Kumar G
Abstract: A device includes first and second circuits. The first circuit includes a temperature sensor to measure a device temperature. The second circuit operates to send an enable signal to the first circuit to cause the temperature sensor to measure the device temperature; and, in response to not receiving at least one of a ready signal and the device temperature from the first circuit within a set amount of time, output a tamper event signal and a timeout event signal, and disable a valid data signal.
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公开(公告)号：US11942962B2
公开(公告)日：2024-03-26
申请号：US17691606
申请日：2022-03-10
Applicant: Texas Instruments Incorporated
Inventor： Anand Kumar G , Srinivasa Chakravarthy
CPC classification number: H03M1/12 , H03M1/00 , G06F3/0604 , G06F3/0655 , G06F3/0679 , G06F13/00 , G06F13/28 , G06F2213/28
Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed. An example apparatus includes interface circuitry to receive an analog signal. The example apparatus also includes sequencer circuitry to: determine whether the apparatus is to operate in a single transfer state or a multiple transfer state; access a configuration from a control register in a plurality of control registers; initiate a conversion of the analog signal to a digital value based on the configuration; and write the digital value to a result register in a plurality of result registers based on the determination.
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公开(公告)号：US20230204666A1
公开(公告)日：2023-06-29
申请号：US18175730
申请日：2023-02-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Veeramanikandan Raju , Anand Kumar G , Christy Leigh She
IPC: G01R31/3185 , G06F21/45 , G06F21/31 , H04L9/40
CPC classification number: G01R31/318536 , G06F21/45 , G06F21/31 , H04L63/1433
Abstract: A system and method for dynamically protecting against security vulnerabilities in a reconfigurable signal chain. The system includes a signal chain formed from at least a first component connected with a second component. The first component has a set of source outputs and a first authentication block, and the second signal chain component has a set of destination inputs and a second authentication block. The system also includes a signal chain configurator that populates the first authentication block with at least one validated endpoint from the set of destination inputs. A signal chain integrity block, which is communicatively coupled with the first authentication block and the second authentication block, identifies a source-destination pair from one or more endpoint pairs formed from the at least one validated endpoint and the set of source outputs. The signal chain integrity block propagates the source-destination pair to the first authentication block and the second authentication block. The second authentication block authenticates any received input using the source-destination pair.
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Patent Agency Ranking
公开(公告)号：US20230188140A1
公开(公告)日：2023-06-15
申请号：US17949446
申请日：2022-09-21
Applicant: Texas Instruments Incorporated
Inventor： Robin Hoel , Anuvrat Srivastava , Aniruddha P N , Anand Kumar G
Abstract: An example apparatus includes clock divider circuitry configured to divide a system clock by a pre-scaler input to generate a divided clock; counter circuitry configured to increment a system count based on the divided clock; comparison circuitry configured to determine a count difference between the system count and a real-time clock count; and controller circuitry configured to modify the pre-scaler input based on a comparison of the count difference to a threshold value.
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公开(公告)号：US20230129042A1
公开(公告)日：2023-04-27
申请号：US17691606
申请日：2022-03-10
Applicant: Texas Instruments Incorporated
Inventor： Anand Kumar G , Srinivasa Chakravarthy
Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed. An example apparatus includes interface circuitry to receive an analog signal. The example apparatus also includes sequencer circuitry to: determine whether the apparatus is to operate in a single transfer state or a multiple transfer state; access a configuration from a control register in a plurality of control registers; initiate a conversion of the analog signal to a digital value based on the configuration; and write the digital value to a result register in a plurality of result registers based on the determination.
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公开(公告)号：US20230098382A1
公开(公告)日：2023-03-30
申请号：US17565797
申请日：2021-12-30
Applicant: Texas Instruments Incorporated
IPC: H03M1/12
Abstract: A method is provided. In some examples, the method includes receiving, at a sequencer circuit of an analog-to-digital converter (ADC), a first request to perform a first conversion. In addition, the method includes determining, by the sequencer circuit, that the ADC is not busy. The method further includes responsive to determining that the ADC is not busy, and by the sequencer circuit, causing the ADC to perform the first conversion. The method also includes receiving, at the sequencer circuit, a second request to perform a second conversion. The method includes determining, by the sequencer circuit, that the ADC is busy and, responsive to determining that the ADC is busy, and by the sequencer circuit, waiting to cause the ADC to perform the second conversion.
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公开(公告)号：US20230097130A1
公开(公告)日：2023-03-30
申请号：US17482734
申请日：2021-09-23
Applicant: Texas Instruments Incorporated
Inventor： Veeramanikandan RAJU , Anand Kumar G
IPC: H03M1/06
Abstract: An integrated circuit includes an analog-to-digital converter (ADC) having selectable first and second analog channel inputs and a digital output. A window comparator coupled to the digital output. The window comparator configured to compare a digital value on the digital output to first and second threshold values. A programmable clock circuit configured to provide a clock signal to the ADC. A controller that, response to assertion of the trigger signal, is configured to generate a sample rate control signal to the clock circuit to cause the clock circuit to increase the frequency of the clock signal and toggle selection between the first and second analog channel inputs. A result comparison circuit having a comparison input coupled to the digital output. The result comparison circuit is configured to compare a first digital conversion output from the ADC toa second digital conversion output from the ADC.
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公开(公告)号：US11604709B2
公开(公告)日：2023-03-14
申请号：US17409029
申请日：2021-08-23
Applicant: Texas Instruments Incorporated
Inventor： Veeramanikandan Raju , Anand Kumar G
Abstract: Techniques including receiving a first control value, starting a timeout counter based on receiving the first control value, receiving a second control value, determining whether the second control value is received before the timeout counter expires, and based on the determination that the second control value is received before the timeout counter expires: determining whether the first control value is the same as the second control value, and loading the first control value into a set of control registers based on the determination that the first control value is the same as the second control value.
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