公开(公告)号：US20250086127A1

公开(公告)日：2025-03-13

申请号：US18958573

申请日：2024-11-25

Applicant: Texas Instruments Incorporated

Inventor： Geet Govind Modi ,  Sumantra Seth ,  Subhashish Mukherjee

IPC: G06F13/20 ,  G06F1/08

Abstract: A system for data transmission includes a physical (PHY) layer which has a rate detection module which determines an adopted clock rate. The rate detection module provides a rate detection signal indicative of the adopted clock rate. The PHY layer includes a reference clock generator which has an input coupled to receive the rate detection signal and an output to provide a reference clock output. The PHY layer includes a PHY interface which has a first input coupled to receive the reference clock output, a data input and a data output. The PHY interface receives data from a MAC interface at the data input and transmits data to the MAC interface through the data output responsive to the reference clock output.

公开(公告)号：US12189549B2

公开(公告)日：2025-01-07

申请号：US18126602

申请日：2023-03-27

Applicant: Texas Instruments Incorporated

Inventor： Geet Govind Modi ,  Sumantra Seth ,  Subhashish Mukherjee

IPC: G06F13/20 ,  G06F1/08

Abstract: A system for data transmission includes a physical (PHY) layer which has a rate detection module which determines an adopted clock rate. The rate detection module provides a rate detection signal indicative of the adopted clock rate. The PHY layer includes a reference clock generator which has an input coupled to receive the rate detection signal and an output to provide a reference clock output. The PHY layer includes a PHY interface which has a first input coupled to receive the reference clock output, a data input and a data output. The PHY interface receives data from a MAC interface at the data input and transmits data to the MAC interface through the data output responsive to the reference clock output.

公开(公告)号：US11615040B2

公开(公告)日：2023-03-28

申请号：US17390428

申请日：2021-07-30

Applicant: Texas Instruments Incorporated

Inventor： Geet Govind Modi ,  Sumantra Seth ,  Subhashish Mukherjee

IPC: G06F13/20 ,  G06F1/08

Abstract: A system for data transmission includes a physical (PHY) layer which has a rate detection module which determines an adopted clock rate. The rate detection module provides a rate detection signal indicative of the adopted clock rate. The PHY layer includes a reference clock generator which has an input coupled to receive the rate detection signal and an output to provide a reference clock output. The PHY layer includes a PHY interface which has a first input coupled to receive the reference clock output, a data input and a data output. The PHY interface receives data from a MAC interface at the data input and transmits data to the MAC interface through the data output responsive to the reference clock output.

公开(公告)号：US20230035848A1

公开(公告)日：2023-02-02

申请号：US17390428

申请日：2021-07-30

Applicant: Texas Instruments Incorporated

Inventor： Geet Govind Modi ,  Sumantra Seth ,  Subhashish Mukherjee

IPC: G06F13/20 ,  G06F1/08

Abstract: A system for data transmission includes a physical (PHY) layer which has a rate detection module which determines an adopted clock rate. The rate detection module provides a rate detection signal indicative of the adopted clock rate. The PHY layer includes a reference clock generator which has an input coupled to receive the rate detection signal and an output to provide a reference clock output. The PHY layer includes a PHY interface which has a first input coupled to receive the reference clock output, a data input and a data output. The PHY interface receives data from a MAC interface at the data input and transmits data to the MAC interface through the data output responsive to the reference clock output.

公开(公告)号：US20240322927A1

公开(公告)日：2024-09-26

申请号：US18346019

申请日：2023-06-30

Applicant: Texas Instruments Incorporated

Inventor： Kalpesh Laxmanbhai Rajai ,  Sankar Prasad Debnath ,  Geet Govind Modi

IPC: H04J3/06

CPC classification number: H04J3/0664 ,  H04J3/0682

Abstract: Systems, apparatus, articles of manufacture, and methods are described for precise timestamping of an Ethernet frame. In some implementations, a device may include network interface circuitry; logic circuitry configured to execute instructions to cause the logic circuitry to: determine a first delay introduced by a physical coding sublayer circuitry at a first time; adjust a first timestamp associated with a first transmission based on the first delay, the first timestamp transmitted with the first transmission; determine a second delay introduced by the physical coding sublayer circuitry at a second time, the second delay different than the first delay; and adjust a second timestamp associated with a second transmission based on the second delay, the second timestamp transmitted with the second transmission.

公开(公告)号：US20230229607A1

公开(公告)日：2023-07-20

申请号：US18126602

申请日：2023-03-27

Applicant: Texas Instruments Incorporated

Inventor： Geet Govind Modi ,  Sumantra Seth ,  Subhashish Mukherjee

IPC: G06F13/20 ,  G06F1/08

CPC classification number: G06F13/20 ,  G06F1/08

Abstract: A system for data transmission includes a physical (PHY) layer which has a rate detection module which determines an adopted clock rate. The rate detection module provides a rate detection signal indicative of the adopted clock rate. The PHY layer includes a reference clock generator which has an input coupled to receive the rate detection signal and an output to provide a reference clock output. The PHY layer includes a PHY interface which has a first input coupled to receive the reference clock output, a data input and a data output. The PHY interface receives data from a MAC interface at the data input and transmits data to the MAC interface through the data output responsive to the reference clock output.

公开(公告)号：US11695539B1

公开(公告)日：2023-07-04

申请号：US17587241

申请日：2022-01-28

Applicant: Texas Instruments Incorporated

Inventor： Geet Govind Modi ,  Sumantra Seth ,  Vikram Sharma ,  Shankar Ramakrishnan ,  Raghu Ganesan

IPC: H04B1/38 ,  H04L5/16 ,  H04L7/033 ,  H04L7/06 ,  H04L7/00 ,  H03K19/173 ,  H04L7/04 ,  H03K19/17784

CPC classification number: H04L7/033 ,  H03K19/1737 ,  H03K19/17784 ,  H04L7/0079 ,  H04L7/0091 ,  H04L7/048 ,  H04L7/065

Abstract: A physical layer transceiver and a network node including the transceiver. The transceiver includes a media independent interface, a converter circuit block comprising circuitry configured to convert digital signals to analog signals for transmission over a network communications medium and convert analog signals received over the medium to digital signals, and one or more processing blocks configured to process digital data communicated between the media independent interface and the converter circuit block according to a network protocol. Management and control circuitry including power management circuitry and reset circuitry are provided. The transceiver further includes at least one single event effect (SEE) monitor, such as an ambience monitor, a configuration register monitor, a state machine monitor, or a phase locked loop (PLL) lock monitor, configured to detect and respond to an SEE event in the transceiver.