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公开(公告)号：US10243463B2
公开(公告)日：2019-03-26
申请号：US15729366
申请日：2017-10-10
Applicant: Texas Instruments Incorporated
Inventor： Yueming Sun , Yihan Yao
IPC: H02M3/158
Abstract: An apparatus comprises a voltage supply configured to provide an input voltage, a buck-boost converter coupled to the voltage supply and comprising an inductor, and a buck-boost controller coupled to the power supply and the buck-boost converter. The buck-boost controller comprises a mode controller coupled to the buck-boost converter and a comparator coupled to the mode controller and the buck-boost converter. The comparator is configured to compare an error signal based on an output voltage of the buck boost-converter to an output current of the inductor to produce a control signal. The mode controller is configured to control the output voltage at least in part according to the control signal.
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公开(公告)号：US20250132670A1
公开(公告)日：2025-04-24
申请号：US18491368
申请日：2023-10-20
Applicant: Texas Instruments Incorporated
Inventor： Yueming Sun , Yuqing Wu
Abstract: Current balancing techniques. In an example, a circuit includes a synchronization terminal, an error amplifier, and a clock generator. The error amplifier is configured to generate a first control voltage signal based on a reference voltage and a power converter output voltage. The clock generator is configured to produce an outgoing clock signal having an outgoing clock frequency. The circuit further includes an encoder, a frequency detector, and a decoder. The encoder is coupled to the clock generator and synchronization terminal, and configured to encode the outgoing clock signal based on the first control voltage signal to provide, at synchronization terminal, an outgoing encoded clock signal. The frequency detector is coupled to synchronization terminal and configured to derive, from an incoming encoded clock signal, an incoming clock frequency. The decoder is coupled to synchronization terminal and configured to derive, from the incoming encoded clock signal, a second control voltage signal.
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公开(公告)号：US20200014299A1
公开(公告)日：2020-01-09
申请号：US16200254
申请日：2018-11-26
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Yueming Sun
IPC: H02M3/158
Abstract: A circuit includes a power stage circuit configured to perform power conversion of an input voltage to provide an output voltage at an output. The circuit further includes a driver circuit configured to drive the power stage circuit to provide the output voltage. The circuit further includes a load transient dynamic compensator configured to detect a rate of change in the output voltage during load transient and to supply a compensating signal based on the rate of change. The circuit further includes a feedback control circuit configured to generate a series of pulses to control the driver circuit based on the output voltage and the compensating signal.
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公开(公告)号：US20240313768A1
公开(公告)日：2024-09-19
申请号：US18306378
申请日：2023-04-25
Applicant: Texas Instruments Incorporated
Inventor： Sri Navaneethakrishnan Easwaran , Angelo Pereira , Yueming Sun , Kae Wong , Ahmed E Hashim , Artur Lewinski
IPC: H03K17/687 , H03K17/10 , H03K17/567
CPC classification number: H03K17/687 , H01L27/02 , H03K17/102 , H03K17/567
Abstract: Described embodiments include a voltage converter power circuit having a high-voltage rated first transistor with a first current terminal coupled to an input voltage terminal, and a second current terminal. A second transistor, a low-voltage rated transistor, has a second control terminal, a third current terminal coupled to the second current terminal, and a fourth current terminal coupled to a switching terminal. A third transistor, a high-voltage rated transistor, has a fifth current terminal coupled to the switching terminal, a sixth current terminal, and a third control terminal. A fourth transistor, a low-voltage rated transistor, is coupled between the sixth current terminal and a ground terminal. A bleeder circuit is coupled between the seventh and eighth current terminals and is configured to prevent a voltage across the fourth transistor from exceeding a breakdown voltage.
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公开(公告)号：US11081957B2
公开(公告)日：2021-08-03
申请号：US16781680
申请日：2020-02-04
Applicant: Texas Instruments Incorporated
Inventor： Guofeng Jin , Yueming Sun
Abstract: A converter circuit includes a power stage circuit configured to convert an input voltage to an output voltage provided at an output, and a control circuit configured to control the power stage circuit. The control circuit is configured to operate in one of a pulse frequency modulation (“PFM”) mode and a pulse width modulation (“PWM”) mode depending on a current supplied to the output. The control circuit includes a multi-mode timer circuit configured to provide a switching signal to set an off time for each switching cycle of the power stage circuit during the PFM mode and during the PWM mode.
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Patent Agency Ranking
公开(公告)号：US11011984B2
公开(公告)日：2021-05-18
申请号：US16200254
申请日：2018-11-26
Applicant: Texas Instruments Incorporated
Inventor： Yueming Sun
IPC: H02M3/158
Abstract: A circuit includes a power stage circuit configured to perform power conversion of an input voltage to provide an output voltage at an output. The circuit further includes a driver circuit configured to drive the power stage circuit to provide the output voltage. The circuit further includes a load transient dynamic compensator configured to detect a rate of change in the output voltage during load transient and to supply a compensating signal based on the rate of change. The circuit further includes a feedback control circuit configured to generate a series of pulses to control the driver circuit based on the output voltage and the compensating signal.
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公开(公告)号：US11496050B2
公开(公告)日：2022-11-08
申请号：US17204360
申请日：2021-03-17
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Xufeng Wu , Wei Zhao , Yueming Sun
Abstract: A device includes a first FET coupled between first and drive terminals, and is configured to turn on/off responsive to a PWM signal having a first/second state, respectively. A second FET is coupled between the first and drive terminals and is configured to turn on responsive to the PWM signal having the first state, and turn off responsive to expiration of a particular delay after the second FET turns on. A third FET is coupled between drive and second terminals, and is configured to turn on/off responsive to the PWM signal having the second/first state, respectively. A fourth FET is coupled between the drive and second terminals, and is configured to turn on responsive to the PWM signal having the second state if a switching terminal has a first voltage, and turn off responsive to the PWM signal having the first state or the switching terminal having a second voltage.
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公开(公告)号：US10608532B1
公开(公告)日：2020-03-31
申请号：US16425353
申请日：2019-05-29
Applicant: Texas Instruments Incorporated
Inventor： Guofeng Jin , Yueming Sun
Abstract: A converter circuit includes a power stage circuit configured to convert an input voltage to an output voltage provided at an output, and a control circuit configured to control the power stage circuit. The control circuit is configured to operate in one of a pulse frequency modulation (“PFM”) mode and a pulse width modulation (“PWM”) mode depending on a current supplied to the output. The control circuit includes a multi-mode timer circuit configured to provide a switching signal to set an off time for each switching cycle of the power stage circuit during the PFM mode and during the PWM mode.
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公开(公告)号：US11509210B1
公开(公告)日：2022-11-22
申请号：US17347177
申请日：2021-06-14
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Yueming Sun , Guofeng Jin
Abstract: A device includes a comparator having a first comparator input configured to receive a time signal. The device also includes a subtractor having a subtractor output coupled to a second comparator input, and a first subtractor input adapted to be coupled to a voltage converter terminal. The device also includes a current source having an output coupled to a second subtractor input, and a current source input coupled to the first subtractor input. The device also includes a capacitor coupled to the second subtractor input and to ground. The device also includes a latch having an output and first and second inputs. The latch output is coupled to a control terminal of a transistor in parallel with the capacitor, the first latch input is coupled to the comparator output, and the second latch input is configured to receive a clock signal.
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公开(公告)号：US20200228009A1
公开(公告)日：2020-07-16
申请号：US16781680
申请日：2020-02-04
Applicant: Texas Instruments Incorporated
Inventor： Guofeng Jin , Yueming Sun
Abstract: A converter circuit includes a power stage circuit configured to convert an input voltage to an output voltage provided at an output, and a control circuit configured to control the power stage circuit. The control circuit is configured to operate in one of a pulse frequency modulation (“PFM”) mode and a pulse width modulation (“PWM”) mode depending on a current supplied to the output. The control circuit includes a multi-mode timer circuit configured to provide a switching signal to set an off time for each switching cycle of the power stage circuit during the PFM mode and during the PWM mode.
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