公开(公告)号：US06480055B2

公开(公告)日：2002-11-12

申请号：US09822028

申请日：2001-03-29

申请人： Thomas Böhm ,  Georg Braun ,  Heinz Hönigschmid ,  Zoltan Manyoki ,  Ernst Neuhold ,  Thomas Röhr

发明人： Thomas Böhm ,  Georg Braun ,  Heinz Hönigschmid ,  Zoltan Manyoki ,  Ernst Neuhold ,  Thomas Röhr

IPC分类号： H03K1776

CPC分类号： G11C5/143 ,  G11C8/08 ,  G11C16/12 ,  H03K19/09425 ,  H03M5/16

摘要： A decoder element is provided with an output, whereby an output signal with one of three different possible potentials is produced. The output signal may have a value of either a first potential, a second potential, and a third potential, where the second potential lies between the first potential and the third potential. The output signal is produced according to voltage values of input signals at terminal connections of the decoder element.

摘要翻译： 解码器元件设置有输出，由此产生具有三种不同可能电位之一的输出信号。 输出信号可以具有第一电位，第二电位和第三电位的值，其中第二电位位于第一电位和第三电位之间。 输出信号根据解码器元件的端子连接处的输入信号的电压值而产生。

公开(公告)号：US06525974B2

公开(公告)日：2003-02-25

申请号：US09888023

申请日：2001-06-22

申请人： Ernst Neuhold ,  Heinz Hönigschmid ,  Georg Braun ,  Zoltan Manyoki ,  Thomas Böhm ,  Thomas Röhr

发明人： Ernst Neuhold ,  Heinz Hönigschmid ,  Georg Braun ,  Zoltan Manyoki ,  Thomas Böhm ,  Thomas Röhr

IPC分类号： G11C700

CPC分类号： G11C29/808 ,  G11C29/846

摘要： An integrated memory contains two normal read amplifiers and two first redundant read amplifiers. It also contains bit lines which are combined into at least two individually addressable normal columns, at least one of which from each normal column is connected to one of the normal read amplifiers. It also has first redundant bit lines which are combined into one individually addressable redundant column, at least one of which is connected to one of the redundant read amplifiers. The first redundant read amplifier and its redundant columns are provided for replacing the two normal read amplifiers and one of the normal columns.

公开(公告)号：US06392445B2

公开(公告)日：2002-05-21

申请号：US09822027

申请日：2001-03-29

申请人： Thomas Röhr ,  Heinz Hönigschmid ,  Zoltan Manyoki ,  Thomas Böhm ,  Georg Braun ,  Ernst Neuhold

发明人： Thomas Röhr ,  Heinz Hönigschmid ,  Zoltan Manyoki ,  Thomas Böhm ,  Georg Braun ,  Ernst Neuhold

IPC分类号： G11C800

CPC分类号： H03M5/16

摘要： The decoder element is used for producing an output signal having three different potentials at an output. The second potential is situated between the first potential and the third potential. The decoder element makes it possible to produce any one of the three potentials at its output based upon the potentials on its connections.

摘要翻译： 解码器元件用于在输出端产生具有三个不同电位的输出信号。 第二电势位于第一电位和第三电位之间。 解码器元件使得可以基于其连接上的电位在其输出端产生三个电位中的任何一个。

公开(公告)号：US06459626B1

公开(公告)日：2002-10-01

申请号：US09962703

申请日：2001-09-24

申请人： Thomas Böhm ,  Georg Braun ,  Heinz Hönigschmid ,  Zoltan Manyoki ,  Thomas Röhr

发明人： Thomas Böhm ,  Georg Braun ,  Heinz Hönigschmid ,  Zoltan Manyoki ,  Thomas Röhr

IPC分类号： G11C700

CPC分类号： G11C7/14 ,  G11C11/22

摘要： An integrated memory has two first switching elements, which respectively connect a bit line of a first bit line pair to a bit line of a second bit line pair. In addition, the integrated memory has two second switching elements, which respectively connect one of the reference cells of one bit line pair to that bit line of the other bit line pair which is not connected via the corresponding first switching element to the bit line assigned to this reference cell. Information is written back to the reference cells via the sense amplifiers. A method of operating the integrated memory is also provided.

公开(公告)号：US06442100B2

公开(公告)日：2002-08-27

申请号：US09904358

申请日：2001-07-12

申请人： Thomas Böhm ,  Georg Braun ,  Heinz Hönigschmid ,  Zoltan Manyoki ,  Thomas Röhr

发明人： Thomas Böhm ,  Georg Braun ,  Heinz Hönigschmid ,  Zoltan Manyoki ,  Thomas Röhr

IPC分类号： G11C800

CPC分类号： G11C7/06 ,  G11C7/1048 ,  G11C11/22

摘要： The integrated memory has m>1 bit lines that are connected to an input of a read-write amplifier via a switching element. Only one switching element is conductively connected for each read or write access. The memory is provided with a switching unit that influences read or write access occurring by way of the read-write amplifier and bit lines. The circuit unit is provided with an activation input. A column-end decoder has a first decoder stage and m second decoder stages. The outputs of the second decoder stages are connected to a control input for each of the switching elements. The output of the first decoder stage is connected to the activation input of the switching unit.

摘要翻译： 集成存储器具有通过开关元件连接到读写放大器的输入的m≥1位线。 每个读或写访问只有一个开关元件被导电连接。 存储器设置有影响通过读写放大器和位线发生的读取或写入访问的切换单元。 电路单元具有激活输入。 列端解码器具有第一解码器级和m个第二解码器级。 第二解码器级的输出端连接到每个开关元件的控制输入端。 第一解码器级的输出连接到开关单元的启动输入。

公开(公告)号：US06255855B1

公开(公告)日：2001-07-03

申请号：US09470310

申请日：1999-12-22

申请人： Heinz Hönigschmid ,  Georg Braun ,  Zoltan Manyoki ,  Thomas Röhr ,  Thomas Böhm

发明人： Heinz Hönigschmid ,  Georg Braun ,  Zoltan Manyoki ,  Thomas Röhr ,  Thomas Böhm

IPC分类号： H03K19084

CPC分类号： G11C8/00 ,  G11C8/10 ,  H03K19/084 ,  H03K19/094 ,  H03K19/23 ,  H03M5/16

摘要： An integrated circuit includes a decoder having an output terminal and five input terminals. The decoder has three operating states including a first operating state for generating a first potential at the output terminal, a second operating state for generating a second potential at the output terminal, and a third operating state for generating a third potential at the output terminal. The second potential lies between the first potential and the third potential.

摘要翻译： 集成电路包括具有输出端和五个输入端的解码器。 解码器具有三个操作状态，包括用于在输出端产生第一电位的第一操作状态，用于在输出端产生第二电位的第二操作状态和用于在输出端产生第三电位的第三操作状态。 第二个潜力位于第一个潜力和第三个潜力之间。

公开(公告)号：US06487128B2

公开(公告)日：2002-11-26

申请号：US09962411

申请日：2001-09-24

申请人： Thomas Böhm ,  Heinz Hönigschmid ,  Thomas Röhr ,  Georg Braun ,  Zoltan Manyoki

发明人： Thomas Böhm ,  Heinz Hönigschmid ,  Thomas Röhr ,  Georg Braun ,  Zoltan Manyoki

IPC分类号： G11C700

CPC分类号： G11C11/22 ,  G11C7/14

摘要： The memory has identically constructed memory cells and reference cells. An item of reference information is written into the reference cells by uncoupling the reference cells from the read amplifiers via first switching elements, and by electrically connecting the part of the bit lines that is connected to the reference cells via second switching elements to a potential line carrying the reference information.

摘要翻译： 存储器具有相同构造的存储器单元和参考单元。 通过经由第一开关元件将读取放大器的参考单元解耦，并且经由第二开关元件将连接到参考单元的位线的一部分电连接到电位线，将参考信息项写入参考单元 携带参考信息。

公开(公告)号：US06538950B2

公开(公告)日：2003-03-25

申请号：US09917553

申请日：2001-07-27

申请人： Thomas Böhm ,  Heinz Hönigschmid ,  Georg Braun ,  Zoltan Manyoki ,  Stefan Lammers ,  Thomas Rohr

发明人： Thomas Böhm ,  Heinz Hönigschmid ,  Georg Braun ,  Zoltan Manyoki ,  Stefan Lammers ,  Thomas Rohr

IPC分类号： G11C800

CPC分类号： G11C7/06 ,  G11C7/065 ,  G11C7/1006

摘要： An integrated memory has a multiplexer and a differential sense amplifier with a differential input. The differential sense amplifier is connected to three bit lines by the multiplexer. The multiplexer electrically connects the differential input of the sense amplifier to any two of the three bit lines connected to it respectively, in accordance with its activation.

公开(公告)号：US06452852B2

公开(公告)日：2002-09-17

申请号：US09767380

申请日：2001-01-22

申请人： Thomas Böhm ,  Georg Braun ,  Heinz Hönigschmid ,  Thomas Röhr

发明人： Thomas Böhm ,  Georg Braun ,  Heinz Hönigschmid ,  Thomas Röhr

IPC分类号： G11C700

CPC分类号： G11C11/22 ,  G11C11/406

摘要： In a semiconductor memory configuration, a refresh operation is always started by a refresh logic circuit when a comparison circuit determines that there is a specific minimum difference when comparing a characteristic variable of at least one reference memory cell with a reference value (VREF).

摘要翻译： 在半导体存储器配置中，当比较电路确定在将至少一个参考存储单元的特征变量与参考值（VREF）进行比较时确定存在特定最小差异时，刷新逻辑电路总是开始刷新操作。

公开(公告)号：US06351422B2

公开(公告)日：2002-02-26

申请号：US09820235

申请日：2001-03-28

申请人： Thomas Röhr ,  Thomas Böhm ,  Heinz Hönigschmid ,  Georg Braun

发明人： Thomas Röhr ,  Thomas Böhm ,  Heinz Hönigschmid ,  Georg Braun

IPC分类号： G11C700

CPC分类号： G11C11/22 ,  G11C7/12 ,  G11C7/22

摘要： The memory has writable memory cells. In addition, it has a bit line pair which connects the memory cells MC to a differential sense amplifier. A control unit is used for precharging the bit lines in a plurality of steps before one of the memory cells is conductively connected to one of the bit lines for a read access operation. For a write access operation, the control unit carries out no more than some of the bit line precharging steps provided for a read access operation before the sense amplifier transfers data to the bit line pair.

摘要翻译： 内存有可写存储单元。 此外，它具有将存储单元MC连接到差分读出放大器的位线对。 控制单元用于在存储器单元之一导通地连接到用于读访问操作的位线之一之前的多个步骤中对位线进行预充电。 对于写访问操作，在读出放大器将数据传送到位线对之前，控制单元执行不超过为读访问操作提供的一些位线预充电步骤。