公开(公告)号：US20090096038A1

公开(公告)日：2009-04-16

申请号：US12115552

申请日：2008-05-06

Applicant: Ting-Shing Wang

Inventor： Ting-Shing Wang

IPC: H01L27/088

CPC classification number: H01L29/7813 ,  H01L21/823475 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0696

Abstract: A power metal-oxide-semiconductor field-effect transistor (MOSFET) array structure is provided. The power MOSFET array is disposed under a gate pad, and space under the gate pad can be well used to increase device integration. When the array and the conventional power MOSFET array disposed under the source pad are connected to an array pair by using circuit connection region, the same gate pad and source pad can be shared, so as to achieve an objective of increasing device integration.

Abstract translation: 提供功率金属氧化物半导体场效应晶体管（MOSFET）阵列结构。 功率MOSFET阵列设置在栅极焊盘下方，栅极焊盘下方的空间可以很好地用于增加器件集成度。 当通过使用电路连接区域将阵列和设置在源极焊盘下面的常规功率MOSFET阵列连接到阵列对时，可以共享相同的栅极焊盘和源极焊盘，从而达到增加器件集成度的目的。

公开(公告)号：US20050048711A1

公开(公告)日：2005-03-03

申请号：US10711939

申请日：2004-10-14

Applicant: Ting-Shing Wang

Inventor： Ting-Shing Wang

IPC: H01L21/336 ,  H01L21/8238 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94

CPC classification number: H01L27/10841 ,  H01L27/0207 ,  H01L27/10832 ,  H01L27/10861 ,  H01L27/10864 ,  H01L27/10867 ,  H01L27/10888 ,  H01L29/945

Abstract: A dynamic random access memory (DRAM) cell is described, including a semiconductor pillar on a substrate, a capacitor on a lower portion of a sidewall of the pillar, and a vertical transistor on an upper portion of the sidewall of the pillar. The capacitor includes a first plate in the lower portion of the sidewall of the pillar, a second plate as an upper electrode at the periphery of the first plate, a third plate at the periphery of the second plate electrically connected with the first plate to form a lower electrode, and a dielectric layer separating the second plate from the first and third plates. A DRAM array based on the DRAM cell and a method for fabricating the DRAM array are also described.

Abstract translation: 描述了动态随机存取存储器（DRAM）单元，其包括衬底上的半导体柱，柱的侧壁的下部的电容器和柱的侧壁上部的垂直晶体管。 所述电容器包括位于所述支柱侧壁下部的第一板，在所述第一板的周边处的作为上部电极的第二板，在所述第二板的外围的第三板与所述第一板电连接以形成 下电极和将第二板与第一和第三板分离的电介质层。 还描述了基于DRAM单元的DRAM阵列和用于制造DRAM阵列的方法。

公开(公告)号：US07435643B2

公开(公告)日：2008-10-14

申请号：US11463896

申请日：2006-08-11

Applicant: Ting-Shing Wang

Inventor： Ting-Shing Wang

IPC: H01L21/8242

CPC classification number: H01L27/10841 ,  H01L27/0207 ,  H01L27/10832 ,  H01L27/10861 ,  H01L27/10864 ,  H01L27/10867 ,  H01L27/10888 ,  H01L29/945

Abstract: A dynamic random access memory (DRAM) cell is described, including a semiconductor pillar on a substrate, a capacitor on a lower portion of a sidewall of the pillar, and a vertical transistor on an upper portion of the sidewall of the pillar. The capacitor includes a first plate in the lower portion of the sidewall of the pillar, a second plate as an upper electrode at the periphery of the first plate, a third plate at the periphery of the second plate electrically connected with the first plate to form a lower electrode, and a dielectric layer separating the second plate from the first and third plates. A DRAM array based on the DRAM cell and a method for fabricating the DRAM array are also described.

Abstract translation: 描述了动态随机存取存储器（DRAM）单元，其包括衬底上的半导体柱，柱的侧壁的下部的电容器和柱的侧壁上部的垂直晶体管。 所述电容器包括位于所述支柱侧壁下部的第一板，在所述第一板的周边处的作为上部电极的第二板，在所述第二板的外围的第三板与所述第一板电连接以形成 下电极和将第二板与第一和第三板分离的电介质层。 还描述了基于DRAM单元的DRAM阵列和用于制造DRAM阵列的方法。

公开(公告)号：US07208789B2

公开(公告)日：2007-04-24

申请号：US11062563

申请日：2005-02-23

Applicant: Ting-Shing Wang

Inventor： Ting-Shing Wang

IPC: H01L29/78

CPC classification number: H01L27/10888 ,  H01L27/10832 ,  H01L27/10861 ,  H01L29/945

Abstract: A memory device that includes a semiconductor substrate, and an array of memory cells, each cell being electrically isolated from adjacent cells and including an island formed from the substrate, the island having a top portion and at least one sidewall portion, and being spaced apart from other islands by a bottom surface on the substrate, a capacitor formed contiguous with the sidewall portion, and a transistor formed on the top portion of the island, the transistor including a gate oxide layer formed on a surface of the top portion, a gate formed on the gate oxide layer, and a first and a second diffused regions formed in the top portion, the first diffused region being spaced apart from the second diffused region.

Abstract translation: 一种存储器件，包括半导体衬底和存储器单元阵列，每个单元与相邻单元电隔离并且包括由衬底形成的岛，所述岛具有顶部部分和至少一个侧壁部分，并且间隔开 通过基板上的底面从其他岛形成与该侧壁部分相邻的电容器，以及形成在该岛的顶部的晶体管，该晶体管包括形成于顶部表面的栅极氧化层，栅极 形成在栅极氧化物层上，以及形成在顶部的第一和第二扩散区域，第一扩散区域与第二扩散区域间隔开。

公开(公告)号：US20050139889A1

公开(公告)日：2005-06-30

申请号：US11062563

申请日：2005-02-23

Applicant: Ting-Shing Wang

Inventor： Ting-Shing Wang

IPC: H01L21/336 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94

CPC classification number: H01L27/10888 ,  H01L27/10832 ,  H01L27/10861 ,  H01L29/945

Abstract: A memory device that includes a semiconductor substrate, and an array of memory cells, each cell being electrically isolated from adjacent cells and including an island formed from the substrate, the island having a top portion and at least one sidewall portion, and being spaced apart from other islands by a bottom surface on the substrate, a capacitor formed contiguous with the sidewall portion, and a transistor formed on the top portion of the island, the transistor including a gate oxide layer formed on a surface of the top portion, a gate formed on the gate oxide layer, and a first and a second diffused regions formed in the top portion, the first diffused region being spaced apart from the second diffused region.

公开(公告)号：US06875653B2

公开(公告)日：2005-04-05

申请号：US10210031

申请日：2002-08-02

Applicant: Ting-Shing Wang

Inventor： Ting-Shing Wang

IPC: H01L21/8242 ,  H01L27/02 ,  H01L27/108

CPC classification number: H01L27/10832 ,  H01L27/0207 ,  H01L27/10867 ,  H01L27/10888

Abstract: A memory device that includes a semiconductor substrate, and an array of memory cells, each cell being electrically isolated from adjacent cells and including an island formed from the substrate, the island having a top portion and at least one sidewall portion, and being spaced apart from other islands by a bottom surface on the substrate, a capacitor formed contiguous with the sidewall portion, and a transistor formed on the top portion of the island, the transistor including a gate oxide layer formed on a surface of the top portion, a gate formed on the gate oxide layer, and a first and a second diffused regions formed in the top portion, the first diffused region being spaced apart from the second diffused region.

Abstract translation: 一种存储器件，包括半导体衬底和存储器单元阵列，每个单元与相邻单元电隔离并且包括由衬底形成的岛，所述岛具有顶部部分和至少一个侧壁部分，并且间隔开 通过基板上的底面从其他岛形成与该侧壁部分相邻的电容器，以及形成在该岛的顶部的晶体管，该晶体管包括形成于顶部表面的栅极氧化层，栅极 形成在栅极氧化物层上，以及形成在顶部的第一和第二扩散区域，第一扩散区域与第二扩散区域间隔开。

公开(公告)号：US07872307B2

公开(公告)日：2011-01-18

申请号：US12115552

申请日：2008-05-06

Applicant: Ting-Shing Wang

Inventor： Ting-Shing Wang

IPC: H01L29/78

CPC classification number: H01L29/7813 ,  H01L21/823475 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0696

Abstract: A power metal-oxide-semiconductor field-effect transistor (MOSFET) array structure is provided. The power MOSFET array is disposed under a gate pad, and space under the gate pad can be well used to increase device integration. When the array and the conventional power MOSFET array disposed under the source pad are connected to an array pair by using circuit connection region, the same gate pad and source pad can be shared, so as to achieve an objective of increasing device integration.

Abstract translation: 提供功率金属氧化物半导体场效应晶体管（MOSFET）阵列结构。 功率MOSFET阵列设置在栅极焊盘下方，栅极焊盘下方的空间可以很好地用于增加器件集成度。 当通过使用电路连接区域将阵列和设置在源极焊盘下面的常规功率MOSFET阵列连接到阵列对时，可以共享相同的栅极焊盘和源极焊盘，从而达到增加器件集成度的目的。

公开(公告)号：US20070004130A1

公开(公告)日：2007-01-04

申请号：US11463896

申请日：2006-08-11

Applicant: Ting-Shing Wang

Inventor： Ting-Shing Wang

IPC: H01L21/8242 ,  H01L29/94

CPC classification number: H01L27/10841 ,  H01L27/0207 ,  H01L27/10832 ,  H01L27/10861 ,  H01L27/10864 ,  H01L27/10867 ,  H01L27/10888 ,  H01L29/945

Abstract: A dynamic random access memory (DRAM) cell is described, including a semiconductor pillar on a substrate, a capacitor on a lower portion of a sidewall of the pillar, and a vertical transistor on an upper portion of the sidewall of the pillar. The capacitor includes a first plate in the lower portion of the sidewall of the pillar, a second plate as an upper electrode at the periphery of the first plate, a third plate at the periphery of the second plate electrically connected with the first plate to form a lower electrode, and a dielectric layer separating the second plate from the first and third plates. A DRAM array based on the DRAM cell and a method for fabricating the DRAM array are also described.

Abstract translation: 描述了动态随机存取存储器（DRAM）单元，其包括衬底上的半导体柱，柱的侧壁的下部的电容器和柱的侧壁上部的垂直晶体管。 所述电容器包括位于所述支柱侧壁下部的第一板，在所述第一板的周边处的作为上部电极的第二板，在所述第二板的外围的第三板与所述第一板电连接以形成 下电极和将第二板与第一和第三板分离的电介质层。 还描述了基于DRAM单元的DRAM阵列和用于制造DRAM阵列的方法。

公开(公告)号：US07119390B2

公开(公告)日：2006-10-10

申请号：US10711939

申请日：2004-10-14

Applicant: Ting-Shing Wang

Inventor： Ting-Shing Wang

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L27/10841 ,  H01L27/0207 ,  H01L27/10832 ,  H01L27/10861 ,  H01L27/10864 ,  H01L27/10867 ,  H01L27/10888 ,  H01L29/945

Abstract: A dynamic random access memory (DRAM) cell is described, including a semiconductor pillar on a substrate, a capacitor on a lower portion of a sidewall of the pillar, and a vertical transistor on an upper portion of the sidewall of the pillar. The capacitor includes a first plate in the lower portion of the sidewall of the pillar, a second plate as an upper electrode at the periphery of the first plate, a third plate at the periphery of the second plate electrically connected with the first plate to form a lower electrode, and a dielectric layer separating the second plate from the first and third plates. A DRAM array based on the DRAM cell and a method for fabricating the DRAM array are also described.

Abstract translation: 描述了动态随机存取存储器（DRAM）单元，其包括衬底上的半导体柱，柱的侧壁的下部的电容器和柱的侧壁上部的垂直晶体管。 所述电容器包括位于所述支柱侧壁下部的第一板，在所述第一板的周边处的作为上部电极的第二板，在所述第二板的外围的第三板与所述第一板电连接以形成 下电极和将第二板与第一和第三板分离的电介质层。 还描述了基于DRAM单元的DRAM阵列和用于制造DRAM阵列的方法。

公开(公告)号：US07026209B2

公开(公告)日：2006-04-11

申请号：US10605199

申请日：2003-09-15

Applicant: Ting-Shing Wang

Inventor： Ting-Shing Wang

IPC: H01L21/8242

CPC classification number: H01L27/10832 ,  H01L27/0207 ,  H01L27/10841 ,  H01L27/10861 ,  H01L27/10864 ,  H01L27/10867 ,  H01L27/10888 ,  H01L29/945

Abstract: A dynamic random access memory (DRAM) cell is described, including a semiconductor pillar on a substrate, a capacitor on a lower portion of a sidewall of the pillar, and a vertical transistor on an upper portion of the sidewall of the pillar. The vertical transistor includes a first doped region, a second doped region, a gate and a gate insulating layer. The first doped region is located in the sidewall and is coupled with the capacitor. The second doped region is located in a top portion of the pillar. The gate is disposed on the sidewall of the pillar between the first and the second doped regions, and the gate insulating layer is disposed between the sidewall and the gate.

Abstract translation: 描述了动态随机存取存储器（DRAM）单元，其包括衬底上的半导体柱，柱的侧壁的下部的电容器和柱的侧壁上部的垂直晶体管。 垂直晶体管包括第一掺杂区，第二掺杂区，栅极和栅极绝缘层。 第一掺杂区域位于侧壁中并与电容器耦合。 第二掺杂区位于柱的顶部。 栅极设置在第一和第二掺杂区域之间的柱的侧壁上，并且栅极绝缘层设置在侧壁和栅极之间。