公开(公告)号：US07573096B2

公开(公告)日：2009-08-11

申请号：US11883939

申请日：2005-02-16

申请人： Toshiyuki Takemori ,  Yuji Watanabe ,  Fuminori Sasaoka ,  Kazushige Matsuyama ,  Kunihito Ohshima ,  Masato Itoi

发明人： Toshiyuki Takemori ,  Yuji Watanabe ,  Fuminori Sasaoka ,  Kazushige Matsuyama ,  Kunihito Ohshima ,  Masato Itoi

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/7813 ,  H01L29/66734 ,  H01L29/7805

摘要： MOS FETs are formed by a drain layer 101, a drift layer 102, P-type body areas 103, N+-type source areas 105, gate electrodes 108, a source electrode film 110, and a drain electrode film 111. In parallel to the MOS FETs, the drain layer 101, the drift layer 102, the P−-type diffusion area 109, and the source electrode film 110 form a diode. The source electrode film 110 and the P−-type diffusion area 109 form an Ohmic contact. The total amount of impurities, which function as P-type impurities in each P-type body area 103, is larger than the total amount of impurities, which function as P-type impurities in the P−-type diffusion area 109.

摘要翻译： MOS FET由漏极层101，漂移层102，P型体区域103，N +型源极区域105，栅极电极108，源极电极膜110和漏极电极膜111形成。与 MOS FET，漏极层101，漂移层102，P型扩散区域109和源极电极膜110形成二极管。 源极电极膜110和P型扩散区域109形成欧姆接触。 每个P型体区103中用作P型杂质的杂质的总量大于P型扩散区域109中作为P型杂质的杂质的总量。

公开(公告)号：US20080135925A1

公开(公告)日：2008-06-12

申请号：US11883939

申请日：2005-02-16

申请人： Toshiyuki Takemori ,  Yuji Watanabe ,  Fuminori Sasaoka ,  Kazushige Matsuyama ,  Kunihito Ohshima ,  Masato Itoi

发明人： Toshiyuki Takemori ,  Yuji Watanabe ,  Fuminori Sasaoka ,  Kazushige Matsuyama ,  Kunihito Ohshima ,  Masato Itoi

IPC分类号： H01L27/06

CPC分类号： H01L29/7813 ,  H01L29/66734 ,  H01L29/7805

摘要： MOS FETs are formed by a drain layer 101, a drift layer 102, P-type body areas 103, N+-type source areas 105, gate electrodes 108, a source electrode film 110, and a drain electrode film 111. In parallel to the MOS FETs, the drain layer 101, the drift layer 102, the P−-type diffusion area 109, and the source electrode film 110 form a diode. The source electrode film 110 and the P−-type diffusion area 109 form an Ohmic contact. The total amount of impurities, which function as P-type impurities in each P-type body area 103, is larger than the total amount of impurities, which function as P-type impurities in the P−-type diffusion area 109.

摘要翻译： MOS FET由漏极层101，漂移层102，P型体区域103，N +型源极区域105，栅极电极108，源极电极膜110和漏极 电极膜111。 与MOS FET并联，漏极层101，漂移层102，P +型扩散区域109和源电极膜110形成二极管。 源极电极膜110和P型扩散区域109形成欧姆接触。 每个P型体区域103中用作P型杂质的杂质的总量大于在P型体区域103中作为P型杂质的杂质的总量， 型扩散区域109。

公开(公告)号：US07939886B2

公开(公告)日：2011-05-10

申请号：US12094312

申请日：2005-11-22

申请人： Toshiyuki Takemori ,  Yuji Watanabe ,  Fuminori Sasaoka ,  Kazushige Matsuyama ,  Kunihito Oshima ,  Masato Itoi

发明人： Toshiyuki Takemori ,  Yuji Watanabe ,  Fuminori Sasaoka ,  Kazushige Matsuyama ,  Kunihito Oshima ,  Masato Itoi

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/4238 ,  H01L29/66348 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7805 ,  H01L29/7811

摘要： A trench gate power MOSFET (1) includes: an n−-type epitaxial layer (12); a p-type body region (20) formed in the vicinity of an upper surface of the n−-type epitaxial layer (12); a plurality of trenches (14) formed so as to reach the n−-type epitaxial layer (12) from an upper surface of the p-type body region (20); and gates (18) formed in the trenches (14). In some regions facing the p-type body region (20) in the n−-type epitaxial layer (12), p-type carrier extracting regions (26a, 26b, 26c) are formed. According to the trench gate power MOSFET (1), holes generated in a cell region can be effectively collected through the p-type carrier extracting regions (26a, 26b, 26c) so as to further increase a speed of the switching operation.

摘要翻译： 沟槽栅极功率MOSFET（1）包括：n型外延层（12）; 形成在所述n型外延层（12）的上表面附近的p型体区（20）。 形成为从p型体区域（20）的上表面到达n型外延层（12）的多个沟槽（14）。 和形成在沟槽（14）中的门（18）。 在n型外延层（12）中面向p型体区（20）的一些区域中，形成p型载流子提取区（26a，26b，26c）。 根据沟槽栅功率MOSFET（1），可以通过p型载流子提取区（26a，26b，26c）有效地收集在单元区域中产生的空穴，从而进一步提高开关动作的速度。

公开(公告)号：US20080315301A1

公开(公告)日：2008-12-25

申请号：US12094312

申请日：2005-11-22

申请人： Toshiyuki Takemori ,  Yuji Watanabe ,  Fuminori Sasaoka ,  Kazushige Matsuyama ,  Kunihito Oshima ,  Masato Itoi

发明人： Toshiyuki Takemori ,  Yuji Watanabe ,  Fuminori Sasaoka ,  Kazushige Matsuyama ,  Kunihito Oshima ,  Masato Itoi

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/4238 ,  H01L29/66348 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7805 ,  H01L29/7811

摘要： A trench gate power MOSFET (1) includes: an n−-type epitaxial layer (12); a p-type body region (20) formed in the vicinity of an upper surface of the n−-type epitaxial layer (12); a plurality of trenches (14) formed so as to reach the n−-type epitaxial layer (12) from an upper surface of the p-type body region (20); and gates (18) formed in the trenches (14). In some regions facing the p-type body region (20) in the n−-type epitaxial layer (12), p-type carrier extracting regions (26a, 26b, 26c) are formed. According to the trench gate power MOSFET (1), holes generated in a cell region can be effectively collected through the p-type carrier extracting regions (26a, 26b, 26c) so as to further increase a speed of the switching operation.

摘要翻译： 沟槽栅极功率MOSFET（1）包括：n型外延层（12）; 形成在所述n型外延层（12）的上表面附近的p型体区（20）。 形成为从p型体区域（20）的上表面到达n型外延层（12）的多个沟槽（14）。 和形成在沟槽（14）中的门（18）。 在n型外延层（12）中面向p型体区（20）的一些区域中，形成p型载流子提取区（26a，26b，26c）。 根据沟槽栅功率MOSFET（1），可以通过p型载流子提取区（26a，26b，26c）有效地收集在单元区域中产生的空穴，从而进一步提高开关动作的速度。

公开(公告)号：US20090250750A1

公开(公告)日：2009-10-08

申请号：US12066984

申请日：2005-09-21

申请人： Toshiyuki Takemori ,  Yuji Watanabe ,  Fuminori Sasaoka ,  Kazushige Matsuyama ,  Kunihito Oshima ,  Masato Itoi

发明人： Toshiyuki Takemori ,  Yuji Watanabe ,  Fuminori Sasaoka ,  Kazushige Matsuyama ,  Kunihito Oshima ,  Masato Itoi

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7805

摘要： A trench gate power MOSFET (1) of the present invention includes an n-type epitaxial layer (12), gates (18) and MOSFET cells. The gate (18) is disposed in a trench (14) formed in a surface of the n-type epitaxial layer (12). The MOSFET cell is formed on the surface of the n-type epitaxial layer (12) so as to be in contact with side surfaces of the trench (14). The trench gate power MOSFET (1) further includes a p-type isolation region (26) formed on the surface of the n-type epitaxial layer (12) and disposed between the MOSFET cells adjacent to each other in the extending direction of the trench (14) out of the MOSFET cells, and has a pn-junction diode formed between the p-type isolation region (26) and the n-type epitaxial layer (12). According to the trench gate power MOSFET (1) of the present invention, the increase of a diode leakage current with the elevation of temperature can be suppressed.

摘要翻译： 本发明的沟槽栅功率MOSFET（1）包括n型外延层（12），栅极（18）和MOSFET单元。 栅极（18）设置在形成在n型外延层（12）的表面中的沟槽（14）中。 MOSFET单元形成在n型外延层（12）的表面上，以与沟槽（14）的侧表面接触。 沟槽栅功率MOSFET（1）还包括形成在n型外延层（12）的表面上的p型隔离区（26），并设置在沟槽的延伸方向上彼此相邻的MOSFET单元之间 （14），并且在p型隔离区（26）和n型外延层（12）之间形成有pn结二极管。 根据本发明的沟槽栅功率MOSFET（1），可以抑制随着温度升高的二极管漏电流的增加。

公开(公告)号：US07193268B2

公开(公告)日：2007-03-20

申请号：US11033734

申请日：2005-01-13

申请人： Toshiyuki Takemori ,  Fuminori Sasaoka ,  Yuji Watanabe

发明人： Toshiyuki Takemori ,  Fuminori Sasaoka ,  Yuji Watanabe

IPC分类号： H01L29/732

CPC分类号： H01L29/7813 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/4236

摘要： In a semiconductor device in which gate trenches and source trenches are formed, when the semiconductor device is flatly viewed, N+ type source areas are formed in parallel with the gate trenches to ease the miniaturization of the semiconductor device. P+ type diffusion areas are separately formed in a direction orthogonal to the N+ type source areas and the gate trenches. Thus, the N+ type source areas and a P type body layer are formed in a laminated state, but the P+ type diffusion areas are not laminated. Therefore, the structure of a mesa section is extremely simple. Furthermore, gate electrode films are connected to one another by a connection member. Thus, the semiconductor device has such a structure as to easily secure electric connection to each gate electrode film from outside. According to the foregoing structure, it is possible to extremely ease the miniaturization of the semiconductor device.

摘要翻译： 在其中形成栅极沟槽和源极沟槽的半导体器件中，当半导体器件平坦地观看时，N + +型源极区域与栅极沟槽平行地形成，以便于半导体器件的小型化 。 P +型超扩散区分别形成在与N + +型源极区域和栅极沟槽正交的方向上。 因此，层叠状态形成N + +型源极区域和P型体层，但不层叠P + +型扩散区域。 因此，台面部分的结构非常简单。 此外，栅极电极膜通过连接构件彼此连接。 因此，半导体器件具有能够容易地从外部确保与各栅电极膜的电连接的结构。 根据上述结构，可以极大地简化半导体器件的小型化。

公开(公告)号：US20060151828A1

公开(公告)日：2006-07-13

申请号：US11033734

申请日：2005-01-13

申请人： Toshiyuki Takemori ,  Fuminori Sasaoka ,  Yuji Watanabe

发明人： Toshiyuki Takemori ,  Fuminori Sasaoka ,  Yuji Watanabe

IPC分类号： H01L31/072

CPC分类号： H01L29/7813 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/4236

摘要： In a semiconductor device in which gate trenches and source trenches are formed, when the semiconductor device is flatly viewed, N+ type source areas are formed in parallel with the gate trenches to ease the miniaturization of the semiconductor device. P+ type diffusion areas are separately formed in a direction orthogonal to the N+ type source areas and the gate trenches. Thus, the N+ type source areas and a P type body layer are formed in a laminated state, but the P+ type diffusion areas are not laminated. Therefore, the structure of a mesa section is extremely simple. Furthermore, gate electrode films are connected to one another by a connection member. Thus, the semiconductor device has such a structure as to easily secure electric connection to each gate electrode film from outside. According to the foregoing structure, it is possible to extremely ease the miniaturization of the semiconductor device.

摘要翻译： 在形成栅极沟槽和源极沟槽的半导体器件中，当半导体器件被平坦地观看时，N + +型源极区域与栅极沟槽平行地形成，以便于半导体器件的小型化 。 P +型超扩散区分别形成在与N + +型源极区域和栅极沟槽正交的方向上。 因此，层叠状态形成N + +型源极区域和P型体层，但不层叠P + +型扩散区域。 因此，台面部分的结构非常简单。 此外，栅极电极膜通过连接构件彼此连接。 因此，半导体器件具有能够容易地从外部确保与各栅电极膜的电连接的结构。 根据上述结构，可以极大地简化半导体器件的小型化。

公开(公告)号：US20050017294A1

公开(公告)日：2005-01-27

申请号：US10924808

申请日：2004-08-25

申请人： Toshiyuki Takemori ,  Masato Itoi ,  Yuji Watanabe

发明人： Toshiyuki Takemori ,  Masato Itoi ,  Yuji Watanabe

IPC分类号： H01L29/41 ,  H01L21/336 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78 ,  H01L31/0312

CPC分类号： H01L29/7813 ,  H01L29/4232 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/7397

摘要： The capacitance between the gate electrode film and the drain layer of semiconductor device is reduced while keeping the resistance low, with the breakdown voltage of the gate insulating film also being maintained at a sufficient level. A trench 10 is formed with the bottom of the trench at a comparatively shallow position in an N-epitaxial layer 18. The thickness of a bottom surface part 16 of a gate electrode film 11 is formed so as to be thicker than other parts of the gate electrode film 11. Also, when a P type body layer 19 is formed, an interface between the P type body layer 19 and an N-epitaxial layer 18 is located at a deeper position than a bottom end of the gate electrode film 11.

摘要翻译： 在保持电阻低的同时，栅极绝缘膜的击穿电压也保持在足够的水平，减小了半导体器件的栅电极膜和漏极层之间的电容。 沟槽10在N外延层18的相对较浅的位置处形成有沟槽的底部。栅电极膜11的底表面部分16的厚度形成为比其他部分厚 此外，当形成P型体层19时，P型体层19和N外延层18之间的界面位于比栅电极膜11的底端更深的位置。

公开(公告)号：US07102182B2

公开(公告)日：2006-09-05

申请号：US10481016

申请日：2002-11-27

申请人： Toshiyuki Takemori ,  Masato Itoi ,  Yuji Watanabe

发明人： Toshiyuki Takemori ,  Masato Itoi ,  Yuji Watanabe

IPC分类号： H01L29/792

CPC分类号： H01L29/7813 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/7802

摘要： An example semiconductor device is capable of preventing a buried diffusion region formed near the bottom surface of a source trench from diffusing to the extent that it contacts a gate trench in the vicinity of that buried diffusion region even if the accuracy of the photographic step of trench formation is not so high. A side wall is formed on the circumferential side of the source trench and then impurities are injected to the bottom surface of the source trench. When the impurities are heated and diffused, the buried P+-type diffusion region is formed with a width almost identical to the width of the opening of the source trench or smaller than the width of the opening of the source trench. Thus, even when irregularities are generated in the manufacturing step and the buried diffusion region becomes larger than is necessary, it is possible to prevent contact of the buried diffusion region with the gate trench.

摘要翻译： 半导体器件的示例能够防止形成在源沟槽的底表面附近的掩埋扩散区域扩散到与该埋入扩散区域附近的栅极沟槽接触的程度，即使沟槽的照相步骤的精度 形成不是很高。 在源沟槽的周向侧上形成侧壁，然后将杂质注入到源沟槽的底表面。 当杂质被加热和扩散时，掩埋的P + +型扩散区形成为具有与源沟槽的开口的宽度几乎相同的宽度，或者小于开口的宽度 源沟槽。 因此，即使在制造步骤中产生不规则并且掩埋扩散区域变得大于必要时，也可以防止掩埋扩散区域与栅极沟槽的接触。

公开(公告)号：US07397082B2

公开(公告)日：2008-07-08

申请号：US10924808

申请日：2004-08-25

申请人： Toshiyuki Takemori ,  Masato Itoi ,  Yuji Watanabe

发明人： Toshiyuki Takemori ,  Masato Itoi ,  Yuji Watanabe

IPC分类号： H01L29/76 ,  H01L31/062

CPC分类号： H01L29/7813 ,  H01L29/4232 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/7397

摘要： The capacitance between the gate electrode film and the drain layer of semiconductor device is reduced while keeping the resistance low, with the breakdown voltage of the gate insulating film also being maintained at a sufficient level. A trench 10 is formed with the bottom of the trench at a comparatively shallow position in an N-epitaxial layer 18. The thickness of a bottom surface part 16 of a gate electrode film 11 is formed so as to be thicker than other parts of the gate electrode film 11. Also, when a P type body layer 19 is formed, an interface between the P type body layer 19 and an N-epitaxial layer 18 is located at a deeper position than a bottom end of the gate electrode film 11.

摘要翻译： 在保持电阻低的同时，栅极绝缘膜的击穿电压也保持在足够的水平，减小了半导体器件的栅电极膜和漏极层之间的电容。 沟槽10在N外延层18的相对较浅的位置处形成有沟槽的底部。栅电极膜11的底表面部分16的厚度形成为比其他部分厚 此外，当形成P型体层19时，P型体层19和N外延层18之间的界面位于比栅电极膜11的底端更深的位置。