公开(公告)号：US08661388B2

公开(公告)日：2014-02-25

申请号：US12571576

申请日：2009-10-01

申请人： Tung-Chieh Chen ,  Ping-Hung Yu ,  Yao-Wen Chang ,  Fwu-Juh Huang ,  Tien-Yueh Liu

发明人： Tung-Chieh Chen ,  Ping-Hung Yu ,  Yao-Wen Chang ,  Fwu-Juh Huang ,  Tien-Yueh Liu

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A multi-packing tree (MPT) macro placer. The MPT macro placer comprises reading input files in a LEF/DEF format, creating a k-level binary multi-packing tree comprising k branch nodes each corresponding to one level and k+1 packing sub-trees each corresponding to one of the nodes and comprising a group of macros, optimizing the multi-packing tree according to a packing result thereof, and generating output files in a DEF format.

摘要翻译： 多包装树（MPT）宏放样器。 MPT宏放置器包括以LEF / DEF格式读取输入文件，创建包括k个分支节点的k级二进制多重打包树，每个k个分支节点对应于每个对应于一个节点的一个级别和k + 1个打包子树; 包括一组宏，根据其打包结果优化多包装树，并以DEF格式生成输出文件。

公开(公告)号：US20100023910A1

公开(公告)日：2010-01-28

申请号：US12571576

申请日：2009-10-01

申请人： Tung-Chieh Chen ,  Ping-Hung Yu ,  Yao-Wen Chang ,  Fwu-Juh Huang ,  Tien-Yueh Liu

发明人： Tung-Chieh Chen ,  Ping-Hung Yu ,  Yao-Wen Chang ,  Fwu-Juh Huang ,  Tien-Yueh Liu

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A multi-packing tree (MPT) macro placer. The MPT macro placer comprises reading input files in a LEF/DEF format, creating a k-level binary multi-packing tree comprising k branch nodes each corresponding to one level and k+1 packing sub-trees each corresponding to one of the nodes and comprising a group of macros, optimizing the multi-packing tree according to a packing result thereof, and generating output files in a DEF format.

摘要翻译： 多包装树（MPT）宏放样器。 MPT宏放置器包括以LEF / DEF格式读取输入文件，创建包括k个分支节点的k级二进制多重打包树，每个k个分支节点对应于每个对应于一个节点的一个级别和k + 1个打包子树; 包括一组宏，根据其打包结果优化多包装树，并以DEF格式生成输出文件。

公开(公告)号：US20070157146A1

公开(公告)日：2007-07-05

申请号：US11608417

申请日：2006-12-08

申请人： Tung-Chieh Chen ,  Ping-Hung Yu ,  Yao-Wen Chang ,  Fwu-Juh Huang ,  Tien-Yueh Liu

发明人： Tung-Chieh Chen ,  Ping-Hung Yu ,  Yao-Wen Chang ,  Fwu-Juh Huang ,  Tien-Yueh Liu

IPC分类号： G06F17/50 ,  H01L25/00 ,  H03K19/00

CPC分类号： G06F17/5072

摘要： A multi-packing tree (MPT) macro placer. The MPT macro placer comprises reading input files in a LEF/DEF format, creating a k-level binary multi-packing tree comprising k branch nodes each corresponding to one level and k+1 packing sub-trees each corresponding to one of the nodes and comprising a group of macros, optimizing the multi-packing tree according to a packing result thereof, and generating output files in a DEF format.

摘要翻译： 多包装树（MPT）宏放样器。 MPT宏放置器包括以LEF / DEF格式读取输入文件，创建包括k个分支节点的k级二进制多重打包树，每个k个分支节点对应于每个对应于一个节点的一个级别和k + 1个打包子树; 包括一组宏，根据其打包结果优化多包装树，并以DEF格式生成输出文件。

公开(公告)号：US08261223B2

公开(公告)日：2012-09-04

申请号：US13093814

申请日：2011-04-25

申请人： Meng-Kai Hsu ,  Yao-Wen Chang ,  Tung-Chieh Chen

发明人： Meng-Kai Hsu ,  Yao-Wen Chang ,  Tung-Chieh Chen

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5072

摘要： A placer produces a global placement plan specifying positions of cell instances and orientations of macros within an integrated circuit (IC) by initially clusterizing cell instances and macros to form a pyramidal hierarchy of blocks. Then the placer iteratively repeats the declusterization and routability improvement process from the highest level to the lowest level of the hierarchy. An objective function is provided in Cartesian coordinate for representing the position of each movable instance and in polar coordinate for representing the orientation of a macro relative to its the center. For each movable instance and each rotatable macro, its position or orientation is determined by conjugate gradient method to minimize total wire length. Finally, the placer uses a look-ahead legalization technique to rotate rotatable macros to legal orientations and move cell instances to legal positions in the end of global placement.

摘要翻译： 放样器通过最初将单元实例和宏聚类以形成块的锥体层次，产生一个全局放置计划，指定集成电路（IC）中宏的位置和宏的位置。 然后，迭代器迭代地重复从层次结构的最高级别到最低级别的分解和路由改进过程。 在笛卡尔坐标中提供了一个目标函数，用于表示每个可移动实例的位置，并以极坐标表示宏相对于其中心的方向。 对于每个可移动实例和每个可旋转宏，其位置或取向由共轭梯度法确定，以使总线长度最小化。 最后，Placer使用先行合法化技术将可旋转的宏转换为法定方向，并在全局放置结束时将单元格实例移动到合法位置。

公开(公告)号：US07603640B2

公开(公告)日：2009-10-13

申请号：US11550487

申请日：2006-10-18

申请人： Shyh-Chang Lin ,  Tung-Chieh Chen ,  Yao-Wen Chang

发明人： Shyh-Chang Lin ,  Tung-Chieh Chen ,  Yao-Wen Chang

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： To generate a floorplan for an integrated circuit to be formed by a collection of modules interconnected by nets, the floorspace to be occupied by the integrated circuit is partitioned into regions and all of the modules are allocated among those regions. The regions are then iteratively partitioning into smaller progressively smaller regions with modules previously allocated any partitioned region allocated among the regions into which it was partitioned, until each region of the floorplan has been allocated no more than a predetermined maximum number of modules. A separate floorplan is then generated for each region. Neighboring regions are then iteratively merged to create progressively larger regions, until only a single region remains, wherein upon merging any neighboring regions to form a larger merged region, the floorplans of the neighboring regions are merged and refined to create a floorplan for the merged region.

摘要翻译： 为了生成由网络互连的模块的集合形成的集成电路的平面图，将由集成电路占据的楼层空间划分为区域，并且所有模块都被分配在这些区域中。 然后将区域迭代地划分成更小的逐渐变小的区域，其中模块先前分配了在其被分割的区域中分配的任何分区，直到布局图的每个区域已经被分配不超过预定的最大数量的模块。 然后为每个区域生成单独的平面图。 然后迭代地合并相邻区域以创建逐渐更大的区域，直到仅剩下一个区域，其中在合并任何相邻区域以形成更大的合并区域时，相邻区域的平面图被合并和细化以创建合并区域的平面图 。

公开(公告)号：US20080155485A1

公开(公告)日：2008-06-26

申请号：US11550487

申请日：2006-10-18

申请人： Shyh-Chang Lin ,  Tung-Chieh Chen ,  Yao-Wen Chang

发明人： Shyh-Chang Lin ,  Tung-Chieh Chen ,  Yao-Wen Chang

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： To generate a floorplan for an integrated circuit to be formed by a collection of modules interconnected by nets, the floorspace to be occupied by the integrated circuit is partitioned into regions and all of the modules are allocated among those regions. The regions are then iteratively partitioning into smaller progressively smaller regions with modules previously allocated any partitioned region allocated among the regions into which it was partitioned, until each region of the floorplan has been allocated no more than a predetermined maximum number of modules. A separate floorplan is then generated for each region. Neighboring regions are then iteratively merged to create progressively larger regions, until only a single region remains, wherein upon merging any neighboring regions to form a larger merged region, the floorplans of the neighboring regions are merged and refined to create a floorplan for the merged region.

摘要翻译： 为了生成由网络互连的模块的集合形成的集成电路的平面图，将由集成电路占据的楼层空间划分为区域，并且所有模块都被分配在这些区域中。 然后将区域迭代地划分成更小的逐渐变小的区域，其中模块先前分配了在其被分割的区域中分配的任何分区，直到布局图的每个区域已经被分配不超过预定的最大数量的模块。 然后为每个区域生成单独的平面图。 然后迭代地合并相邻区域以创建逐渐更大的区域，直到仅剩下一个区域，其中在合并任何相邻区域以形成更大的合并区域时，相邻区域的平面图被合并和细化以创建合并区域的平面图 。

公开(公告)号：US20110202897A1

公开(公告)日：2011-08-18

申请号：US13093814

申请日：2011-04-25

申请人： Meng-Kai Hsu ,  Yao-Wen Chang ,  Tung-Chieh Chen

发明人： Meng-Kai Hsu ,  Yao-Wen Chang ,  Tung-Chieh Chen

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A placer produces a global placement plan specifying positions of cell instances and orientations of macros within an integrated circuit (IC) by initially clusterizing cell instances and macros to form a pyramidal hierarchy of blocks. Then the placer iteratively repeats the declusterization and routability improvement process from the highest level to the lowest level of the hierarchy. An objective function is provided in Cartesian coordinate for representing the position of each movable instance and in polar coordinate for representing the orientation of a macro relative to its the center. For each movable instance and each rotatable macro, its position or orientation is determined by conjugate gradient method to minimize total wire length. Finally, the placer uses a look-ahead legalization technique to rotate rotatable macros to legal orientations and move cell instances to legal positions in the end of global placement.

摘要翻译： 放样器通过最初将单元实例和宏聚类以形成块的锥体层次，产生一个全局放置计划，指定集成电路（IC）中宏的位置和宏的位置。 然后，迭代器迭代地重复从层次结构的最高级别到最低级别的分解和路由改进过程。 在笛卡尔坐标中提供了一个目标函数，用于表示每个可移动实例的位置，并以极坐标表示宏相对于其中心的方向。 对于每个可移动实例和每个可旋转宏，其位置或取向由共轭梯度法确定，以使总线长度最小化。 最后，Placer使用先行合法化技术将可旋转的宏转换为法定方向，并在全局放置结束时将单元格实例移动到合法位置。

公开(公告)号：US20120304139A1

公开(公告)日：2012-11-29

申请号：US13476027

申请日：2012-05-21

申请人： Tung-Chieh Chen ,  Hung-Ming Chen ,  Yi-Peng Weng

发明人： Tung-Chieh Chen ,  Hung-Ming Chen ,  Yi-Peng Weng

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5072 ,  G06F2217/06

摘要： A method of fast analog layout migration from an original layout is disclosed. Various placement constraints, including topology, matching and symmetry are extracted from the schematic or netlist as well as the original layout. In addition, relative placement patterns are extracted from the original layout for matching and symmetry constraints. A constraint hierarchy tree can be built according to the constraints, and relative placement patterns are attached accordingly. By using the constraint hierarchy tree, multiple new placement results are efficiently explored that preserve the relative placement patterns for matching and symmetry constraints.

摘要翻译： 公开了一种从原始布局进行快速模拟布局迁移的方法。 从原理图或网表以及原始布局中提取各种布局约束，包括拓扑，匹配和对称性。 此外，从原始布局中提取相对放置图案以进行匹配和对称约束。 可以根据约束构建约束层次树，并相应地附加相对布局模式。 通过使用约束层次树，有效地探索了多个新的布局结果，保留了匹配和对称约束的相对布局模式。

公开(公告)号：US20120180014A1

公开(公告)日：2012-07-12

申请号：US13277229

申请日：2011-10-20

申请人： Min-Yi Fang ,  Ssu-Ping Ko ,  Cheng-Ming Wu ,  Chun-Chen Chen ,  Tsung-Ching Lu ,  Tung-Chieh Chen ,  Yu-Chi Su

发明人： Min-Yi Fang ,  Ssu-Ping Ko ,  Cheng-Ming Wu ,  Chun-Chen Chen ,  Tsung-Ching Lu ,  Tung-Chieh Chen ,  Yu-Chi Su

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： A computer-implemented method to perform context-sensitive incremental design rule checking (DRC) for an integrated circuit (IC). An incremental DRC engine checks design rule violations between a set of environment shapes and a set of active shapes. If no design rule violations are found, the set of active shapes will be added into the set of environment shapes. Furthermore, the incremental DRC engine can be embedded into placement tools, routing tools, or interactive layout editing tools to check design rule violations and help generate DRC error free layouts.

摘要翻译： 一种用于为集成电路（IC）执行上下文敏感增量设计规则检查（DRC）的计算机实现的方法。 增量DRC引擎检查一组环境形状和一组活动形状之间的设计规则违规。 如果没有发现违规设计规则，那么活动形状集将被添加到一组环境形状中。 此外，增量DRC引擎可以嵌入到布局工具，路由工具或交互式布局编辑工具中，以检查违规设计规则，并帮助生成DRC无错误布局。

公开(公告)号：US08407647B2

公开(公告)日：2013-03-26

申请号：US12970888

申请日：2010-12-16

申请人： Fong-Yuan Chang ,  Sheng-Hsiung Chen ,  Tung-Chieh Chen ,  Ren-Song Tsay ,  Wai-Kei Mak

发明人： Fong-Yuan Chang ,  Sheng-Hsiung Chen ,  Tung-Chieh Chen ,  Ren-Song Tsay ,  Wai-Kei Mak

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081

摘要： A method for designing and making an integrated circuit is described. That method utilizes statistical models of wire segments to accurately estimate the expected length of minimum-length, orthogonal wire segments within a block. From these estimates, the method accurately estimates an ratio between the horizontal and vertical routing resources required, termed the “H/V Demand Ratio.” From the H/V Demand Ratio, an accurate estimate of the height and width of the block may be determined. Thereafter, placement and routing may be performed quickly and accurately, thereby allowing the block to be designed and manufactured quickly and cost effectively. A method for designing an integrated circuit with efficient metal-1 resource utilization is also described.

摘要翻译： 描述了一种用于设计和制造集成电路的方法。 该方法使用线段的统计模型来精确估计块内最小长度正交线段的预期长度。 从这些估计，该方法准确地估计所需的水平和垂直路由资源之间的比例，称为H / V需求比率。 根据H / V需求比，可以确定块的高度和宽度的准确估计。 此后，可以快速且准确地执行放置和布线，从而允许块被快速且成本有效地设计和制造。 还描述了一种设计具有有效的金属-1资源利用的集成电路的方法。