公开(公告)号：US09269649B2

公开(公告)日：2016-02-23

申请号：US14064219

申请日：2013-10-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chen-Hua Tsai ,  Jian-Cheng Chen ,  Chin-Yueh Tsai ,  Yao-Jen Fan ,  Heng-Kun Chen ,  Hsiang Yang

IPC: G06F17/50 ,  H01L23/48 ,  G03F1/70

CPC classification number: G03F1/70 ,  G06F17/5072 ,  G06F2217/12 ,  H01L21/0334 ,  H01L23/48 ,  H01L23/481 ,  H01L23/528 ,  H01L2924/0002 ,  Y02P90/265 ,  H01L2924/00

Abstract: A method for generating dummy patterns includes providing a layout region having a layout pattern with a first density, inserting a plurality of first dummy patterns with a second density corresponding to the first density in the layout pattern, dividing the layout region into a plurality of sub-regions with a third density, adjusting a size of the first dummy pattern according to a difference between the second density and the third density, and outputting the layout pattern and the first dummy patterns on a photomask.

公开(公告)号：US20160126182A1

公开(公告)日：2016-05-05

申请号：US14993103

申请日：2016-01-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chen-Hua Tsai ,  Jian-Cheng Chen ,  Chin-Yueh Tsai ,  Yao-Jen Fan ,  Heng-Kun Chen ,  Hsiang Yang

IPC: H01L23/528 ,  H01L21/033

CPC classification number: G03F1/70 ,  G06F17/5072 ,  G06F2217/12 ,  H01L21/0334 ,  H01L23/48 ,  H01L23/481 ,  H01L23/528 ,  H01L2924/0002 ,  Y02P90/265 ,  H01L2924/00

Abstract: A semiconductor layout pattern includes a device layout pattern, a plurality of rectangular first dummy patterns having a first size, a plurality of rectangular second dummy patterns having second sizes, and a plurality of bar-like third dummy patterns having varied third sizes. The pattern densities are smartly equalized by positioning the second dummy patterns.

Abstract translation: 半导体布局图案包括器件布局图案，具有第一尺寸的多个矩形第一虚设图案，具有第二尺寸的多个矩形第二虚设图案和具有变化的第三尺寸的多个条形第三虚设图案。 通过定位第二虚拟图案，图案密度被巧妙地均衡。

公开(公告)号：US20140042640A1

公开(公告)日：2014-02-13

申请号：US14065412

申请日：2013-10-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chen-Hua Tsai ,  Jian-Cheng Chen ,  Chin-Yueh Tsai ,  Yao-Jen Fan ,  Heng-Kun Chen ,  Hsiang Yang

IPC: H01L23/48

CPC classification number: G03F1/70 ,  G06F17/5072 ,  G06F2217/12 ,  H01L21/0334 ,  H01L23/48 ,  H01L23/481 ,  H01L23/528 ,  H01L2924/0002 ,  Y02P90/265 ,  H01L2924/00

Abstract: A semiconductor layout pattern includes a device layout pattern, a plurality of rectangular first dummy patterns having a first size, a plurality of rectangular second dummy patterns having varied second sizes, and a plurality of first via dummy patterns smaller than the second dummy patterns and arranged in a spatial range within the second dummy patterns.

Abstract translation: 半导体布局图案包括设备布局图案，具有第一尺寸的多个矩形第一虚设图案，具有变化的第二尺寸的多个矩形第二虚设图案以及比第二虚设图形小的多个第一通孔虚设图案， 在第二虚拟图案内的空间范围内。

公开(公告)号：US20140042636A1

公开(公告)日：2014-02-13

申请号：US14064219

申请日：2013-10-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chen-Hua Tsai ,  Jian-Cheng Chen ,  Chin-Yueh Tsai ,  Yao-Jen Fan ,  Heng-Kun Chen ,  Hsiang Yang

IPC: H01L23/48

CPC classification number: G03F1/70 ,  G06F17/5072 ,  G06F2217/12 ,  H01L21/0334 ,  H01L23/48 ,  H01L23/481 ,  H01L23/528 ,  H01L2924/0002 ,  Y02P90/265 ,  H01L2924/00

Abstract: A method for generating dummy patterns includes providing a layout region having a layout pattern with a first density, inserting a plurality of first dummy patterns with a second density corresponding to the first density in the layout pattern, dividing the layout region into a plurality of sub-regions with a third density, adjusting a size of the first dummy pattern according to a difference between the second density and the third density, and outputting the layout pattern and the first dummy patterns on a photomask.

Abstract translation: 一种用于产生虚拟图案的方法包括提供具有第一密度的布局图案的布局区域，在布局图案中插入具有与第一密度对应的第二密度的多个第一伪图案，将布局区域分成多个子图 具有第三密度的区域，根据第二密度和第三密度之间的差来调整第一伪图案的尺寸，并将布局图案和第一伪图案输出到光掩模上。

公开(公告)号：US09857677B2

公开(公告)日：2018-01-02

申请号：US14993103

申请日：2016-01-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chen-Hua Tsai ,  Jian-Cheng Chen ,  Chin-Yueh Tsai ,  Yao-Jen Fan ,  Heng-Kun Chen ,  Hsiang Yang

IPC: G03F1/70 ,  G06F17/50 ,  H01L21/033 ,  H01L23/48 ,  H01L23/528

CPC classification number: G03F1/70 ,  G06F17/5072 ,  G06F2217/12 ,  H01L21/0334 ,  H01L23/48 ,  H01L23/481 ,  H01L23/528 ,  H01L2924/0002 ,  Y02P90/265 ,  H01L2924/00

Abstract: A semiconductor layout pattern includes a device layout pattern, a plurality of rectangular first dummy patterns having a first size, a plurality of rectangular second dummy patterns having second sizes, and a plurality of bar-like third dummy patterns having varied third sizes. The pattern densities are smartly equalized by positioning the second dummy patterns.

公开(公告)号：US09245822B2

公开(公告)日：2016-01-26

申请号：US14065412

申请日：2013-10-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chen-Hua Tsai ,  Jian-Cheng Chen ,  Chin-Yueh Tsai ,  Yao-Jen Fan ,  Heng-Kun Chen ,  Hsiang Yang

IPC: G03F1/36 ,  H01L23/48 ,  G06F17/50 ,  G03F1/70

CPC classification number: G03F1/70 ,  G06F17/5072 ,  G06F2217/12 ,  H01L21/0334 ,  H01L23/48 ,  H01L23/481 ,  H01L23/528 ,  H01L2924/0002 ,  Y02P90/265 ,  H01L2924/00

Abstract: A semiconductor layout pattern includes a device layout pattern, a plurality of rectangular first dummy patterns having a first size, a plurality of rectangular second dummy patterns having varied second sizes, and a plurality of first via dummy patterns smaller than the second dummy patterns and arranged in a spatial range within the second dummy patterns.

Abstract translation: 半导体布局图案包括设备布局图案，具有第一尺寸的多个矩形第一虚设图案，具有变化的第二尺寸的多个矩形第二虚设图案以及比第二虚设图形小的多个第一通孔虚设图案， 在第二虚拟图案内的空间范围内。