公开(公告)号：US09786654B1

公开(公告)日：2017-10-10

申请号：US15298248

申请日：2016-10-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jhih-Ming Wang ,  Li-Cih Wang ,  Tien-Hao Tang

IPC: H01L23/62 ,  H01L27/02 ,  H01L29/06

CPC classification number: H01L27/0266 ,  H01L27/0262 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/87

Abstract: An ESD protection semiconductor device includes a substrate, a first isolation structure disposed in the substrate, a gate disposed on the substrate and overlapping a portion of the first isolation structure, a source region formed in the substrate at a first side of the gate, and a drain region formed in the substrate at a second side of the gate opposite to the first side. The substrate and the drain region include a first conductivity type, the source region includes a second conductivity type, and the first conductivity and the second conductivity type are complementary to each other.

公开(公告)号：US20180358294A1

公开(公告)日：2018-12-13

申请号：US15667637

申请日：2017-08-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jhih-Ming Wang ,  Li-Cih Wang ,  Tien-Hao Tang

IPC: H01L23/525 ,  H01L23/522

CPC classification number: H01L23/5256 ,  H01L23/5223

Abstract: An electric connector includes a metal interconnect, a first vertical element and a second vertical element. The metal interconnect includes a plurality of horizontal elements. The first vertical element physically connects to a top surface of each of the horizontal elements. The second vertical element physically connects to a bottom surface of each of the horizontal elements, and the second vertical element misaligns the first vertical element. The present invention also provides an electric connector including a first vertical element and a second vertical element. The first vertical element physically connects to a top surface of a horizontal element. The second vertical element physically connects to a bottom surface of the horizontal element, and the second vertical element misaligns the first vertical element, wherein the first vertical element or the horizontal element is burned out before the second vertical element is burned out while a voltage is applied.

公开(公告)号：US09972615B1

公开(公告)日：2018-05-15

申请号：US15351413

申请日：2016-11-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jhih-Ming Wang ,  Li-Cih Wang ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L27/0266 ,  H01L27/0262 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/7835

Abstract: A semiconductor device for ESD protection, includes a drain region, a first doped region, a second doped region and a source region. The drain region is disposed in a substrate at a first side of a gate and the drain region has a first conductivity type. The first doped region is disposed in a second doped well at a second side of the gate and has a second conductivity type. The source region is also disposed in the second doped well and has the first conductive type, and the source region surrounds the first doped region from a topview. The second doped region is disposed in the second doped well and has the second conductive type, and the second doped region is disposed between the gate and the source region, wherein a plurality of contacts is electrically connected to the second doped region.

公开(公告)号：US09607980B1

公开(公告)日：2017-03-28

申请号：US15011681

申请日：2016-02-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jhih-Ming Wang ,  Li-Cih Wang ,  Tien-Hao Tang

IPC: H01L29/66 ,  H01L27/02 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L27/0266 ,  H01L29/0623 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7826

Abstract: The present invention provides a high voltage transistor including a substrate, a first base region having a first conductivity type, and a first doped region, a second doped region, a second base region and a third doped region having a second conductivity type complementary to the first conductivity type. The first base region, the second doped region, the second base region and the third doped region are disposed in the substrate, and the first doped region is disposed in the substrate. The third doped region, the second base region and the second doped region are stacked sequentially, and the doping concentrations of the third doped region, the second base region and the second doped region gradually increase.

公开(公告)号：US09613948B1

公开(公告)日：2017-04-04

申请号：US15273682

申请日：2016-09-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jhih-Ming Wang ,  Li-Cih Wang ,  Tien-Hao Tang

IPC: H01L27/00 ,  H01L27/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L27/0266 ,  H01L27/0248 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/7816 ,  H01L29/7835

Abstract: An ESD protection semiconductor device includes a substrate, a first isolation structure formed in the substrate, a gate disposed on the substrate, a source region formed in the substrate a first side of the gate, a first doped region formed in the substrate at a second side of the gate opposite to the first side, and a drain region formed in the first doped region. The gate overlaps a portion of the first isolation structure. The drain region is spaced apart from the first isolation by a portion of the first doped region. The substrate includes a first conductivity type, the source region, and the first doped region and the drain region include a second conductivity type. And the second conductivity type is complementary to the first conductivity type.

公开(公告)号：US09343567B2

公开(公告)日：2016-05-17

申请号：US14454739

申请日：2014-08-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Ning He ,  Jhih-Ming Wang ,  Lu-An Chen ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L27/02 ,  H01L29/10

CPC classification number: H01L29/7816 ,  H01L27/0248 ,  H01L27/0262 ,  H01L27/027 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/0886 ,  H01L29/1083

Abstract: A semiconductor device is includes a substrate, a gate positioned on the substrate, and a drain region and a source region formed at two respective sides of the gate in the substrate. The drain region includes a first doped region having a first conductivity type, a second doped region having a second conductivity type, and a third doped region. The first conductivity type and the second conductivity type are complementary to each other. The semiconductor device further includes a first well region formed under the first doped region, a second well region formed under the second doped region, and a third well region formed under the third doped region. The first well region, the second well region, and the third well region all include the first conductivity type. A concentration of the second well region is different from a concentration of the third well region.

Abstract translation: 半导体器件包括衬底，位于衬底上的栅极和形成在衬底中的栅极的两个相应侧的漏极区域和源极区域。 漏区包括具有第一导电类型的第一掺杂区，具有第二导电类型的第二掺杂区和第三掺杂区。 第一导电类型和第二导电类型彼此互补。 半导体器件还包括形成在第一掺杂区下的第一阱区，形成在第二掺杂区下的第二阱区，以及形成在第三掺杂区下的第三阱区。 第一阱区域，第二阱区域和第三阱区域都包括第一导电类型。 第二阱区域的浓度不同于第三阱区域的浓度。

公开(公告)号：US10262940B2

公开(公告)日：2019-04-16

申请号：US15667637

申请日：2017-08-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jhih-Ming Wang ,  Li-Cih Wang ,  Tien-Hao Tang

IPC: H01L23/52 ,  H01L23/525 ,  H01L23/522

Abstract: An electric connector includes a metal interconnect, a first vertical element and a second vertical element. The metal interconnect includes a plurality of horizontal elements. The first vertical element physically connects to a top surface of each of the horizontal elements. The second vertical element physically connects to a bottom surface of each of the horizontal elements, and the second vertical element misaligns the first vertical element. The present invention also provides an electric connector including a first vertical element and a second vertical element. The first vertical element physically connects to a top surface of a horizontal element. The second vertical element physically connects to a bottom surface of the horizontal element, and the second vertical element misaligns the first vertical element, wherein the first vertical element or the horizontal element is burned out before the second vertical element is burned out while a voltage is applied.

公开(公告)号：US20180138166A1

公开(公告)日：2018-05-17

申请号：US15351413

申请日：2016-11-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jhih-Ming Wang ,  Li-Cih Wang ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/0266 ,  H01L27/0262 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/7835

Abstract: A semiconductor device for ESD protection, includes a drain region, a first doped region, a second doped region and a source region. The drain region is disposed in a substrate at a first side of a gate and the drain region has a first conductivity type. The first doped region is disposed in a second doped well at a second side of the gate and has a second conductivity type. The source region is also disposed in the second doped well and has the first conductive type, and the source region surrounds the first doped region from a topview. The second doped region is disposed in the second doped well and has the second conductive type, and the second doped region is disposed between the gate and the source region, wherein a plurality of contacts is electrically connected to the second doped region.

公开(公告)号：US20160043216A1

公开(公告)日：2016-02-11

申请号：US14454739

申请日：2014-08-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Ning He ,  Jhih-Ming Wang ,  Lu-An Chen ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L29/78 ,  H01L29/10

CPC classification number: H01L29/7816 ,  H01L27/0248 ,  H01L27/0262 ,  H01L27/027 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/0886 ,  H01L29/1083

Abstract: A semiconductor device is includes a substrate, a gate positioned on the substrate, and a drain region and a source region formed at two respective sides of the gate in the substrate. The drain region includes a first doped region having a first conductivity type, a second doped region having a second conductivity type, and a third doped region. The first conductivity type and the second conductivity type are complementary to each other. The semiconductor device further includes a first well region formed under the first doped region, a second well region formed under the second doped region, and a third well region formed under the third doped region. The first well region, the second well region, and the third well region all include the first conductivity type. A concentration of the second well region is different from a concentration of the third well region.

Abstract translation: 半导体器件包括衬底，位于衬底上的栅极和形成在衬底中的栅极的两个相应侧的漏极区域和源极区域。 漏区包括具有第一导电类型的第一掺杂区，具有第二导电类型的第二掺杂区和第三掺杂区。 第一导电类型和第二导电类型彼此互补。 半导体器件还包括形成在第一掺杂区下的第一阱区，形成在第二掺杂区下的第二阱区，以及形成在第三掺杂区下的第三阱区。 第一阱区域，第二阱区域和第三阱区域都包括第一导电类型。 第二阱区域的浓度不同于第三阱区域的浓度。