公开(公告)号：US12092666B1

公开(公告)日：2024-09-17

申请号：US18120383

申请日：2023-03-11

申请人： INNOVISION SEMICONDUCTOR INC

发明人： Haiyin Li

IPC分类号： G01R19/32 ,  G01R19/00 ,  H01L29/78 ,  H03K17/14

CPC分类号： G01R19/32 ,  G01R19/0092 ,  H01L29/7815 ,  H01L29/7826 ,  H03K17/145 ,  H03K2217/0027

摘要： A power stage, comprising of multiple power MOSFETs and control and monitoring circuits, is an important part of voltage regulators. The voltage regulator controller typically monitors the power stage output current to implement control and protection functions. Traditional power stages mostly adapt monolithic solutions, suffering from performance inefficiencies due to the LDMOS process, while co-packaged solutions with combined VDMOS and LDMOS processes suffer from potential large current monitoring errors due to different operating temperatures. The current invention proposes a current monitoring circuit with temperature compensation to cancel the temperature coefficient mismatch between the external power MOSFET and the current monitoring circuit. Therefore, the gain of the current monitoring circuit doesn't change with the temperature, allowing for high current monitoring precision, and the temperature compensation circuit doesn't affect the bandwidth of the current monitoring circuit, allowing the use of the output current monitoring signal for close-loop control and over-current protection.

公开(公告)号：US10002959B2

公开(公告)日：2018-06-19

申请号：US15429282

申请日：2017-02-10

申请人： Infineon Technologies AG

发明人： Andreas Meiser ,  Till Schloesser

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L23/528 ,  H01L29/66 ,  H01L23/34

CPC分类号： H01L29/7804 ,  H01L23/34 ,  H01L23/5283 ,  H01L27/0705 ,  H01L27/0727 ,  H01L29/0646 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41708 ,  H01L29/4175 ,  H01L29/42304 ,  H01L29/4236 ,  H01L29/66712 ,  H01L29/732 ,  H01L29/7813 ,  H01L29/7826 ,  H01L29/7835 ,  H01L29/8613

摘要： A semiconductor device includes a transistor in a semiconductor substrate having a first main surface. The transistor includes a source region, a source contact, the source contact including a first and second source contact portion, and a gate electrode in a gate trench in the first main surface adjacent to a body region. The body region and a drift zone are disposed along a first direction parallel to the first main surface between the source region and a drain region. The second source contact portion is disposed at a second main surface of the semiconductor substrate. The first source contact portion includes a source conductive material in direct contact with the source region, the first source contact portion further including a portion of the semiconductor substrate between the source conductive material and the second source contact portion. The semiconductor device further includes a temperature sensor in the semiconductor substrate.

公开(公告)号：US20170317176A1

公开(公告)日：2017-11-02

申请号：US15646152

申请日：2017-07-11

申请人： Infineon Technologies AG

发明人： Andreas Meiser ,  Rolf Weis ,  Franz Hirler ,  Martin Vielemeyer ,  Markus Zundel ,  Peter Irsigler

IPC分类号： H01L29/417 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L27/12

CPC分类号： H01L29/4175 ,  H01L27/1203 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66696 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/7826 ,  H01L29/7835

摘要： A semiconductor device includes a transistor in a semiconductor body having a first main surface. The transistor includes: a source contact electrically connected to a source region; a drain contact electrically connected to a drain region; a gate electrode at the channel region, the channel region and a drift zone disposed along a first direction between the source and drain regions, the first direction being parallel to the first main surface, the channel region patterned into a ridge by adjacent gate trenches formed in the first main surface, the adjacent gate trenches spaced apart in a second direction perpendicular to the first direction, a longitudinal axis of the ridge extending in the first direction and a longitudinal axis of the gate trenches extending in the first direction; and at least one of the source and drain contacts being adjacent to a second main surface opposite the first main surface.

公开(公告)号：US20170236931A1

公开(公告)日：2017-08-17

申请号：US15429282

申请日：2017-02-10

申请人： Infineon Technologies AG

发明人： Andreas MEISER ,  Till SCHLOESSER

IPC分类号： H01L29/78 ,  H01L23/34 ,  H01L23/528 ,  H01L29/66 ,  H01L29/10 ,  H01L29/423

CPC分类号： H01L29/7804 ,  H01L23/34 ,  H01L23/5283 ,  H01L27/0705 ,  H01L27/0727 ,  H01L29/0646 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41708 ,  H01L29/4175 ,  H01L29/42304 ,  H01L29/4236 ,  H01L29/66712 ,  H01L29/732 ,  H01L29/7813 ,  H01L29/7826 ,  H01L29/7835 ,  H01L29/8613

摘要： A semiconductor device includes a transistor in a semiconductor substrate having a first main surface. The transistor includes a source region, a source contact, the source contact including a first and second source contact portion, and a gate electrode in a gate trench in the first main surface adjacent to a body region. The body region and a drift zone are disposed along a first direction parallel to the first main surface between the source region and a drain region. The second source contact portion is disposed at a second main surface of the semiconductor substrate. The first source contact portion includes a source conductive material in direct contact with the source region, the first source contact portion further including a portion of the semiconductor substrate between the source conductive material and the second source contact portion. The semiconductor device further includes a temperature sensor in the semiconductor substrate.

公开(公告)号：US09607980B1

公开(公告)日：2017-03-28

申请号：US15011681

申请日：2016-02-01

申请人： UNITED MICROELECTRONICS CORP.

发明人： Jhih-Ming Wang ,  Li-Cih Wang ,  Tien-Hao Tang

IPC分类号： H01L29/66 ,  H01L27/02 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06

CPC分类号： H01L27/0266 ,  H01L29/0623 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7826

摘要： The present invention provides a high voltage transistor including a substrate, a first base region having a first conductivity type, and a first doped region, a second doped region, a second base region and a third doped region having a second conductivity type complementary to the first conductivity type. The first base region, the second doped region, the second base region and the third doped region are disposed in the substrate, and the first doped region is disposed in the substrate. The third doped region, the second base region and the second doped region are stacked sequentially, and the doping concentrations of the third doped region, the second base region and the second doped region gradually increase.

公开(公告)号：US09559199B2

公开(公告)日：2017-01-31

申请号：US14574707

申请日：2014-12-18

申请人： Silanna Asia Pte Ltd

发明人： George Imthurn ,  James Ballard ,  Yashodhan Moghe

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/40

CPC分类号： H01L29/402 ,  G01R19/0092 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66681 ,  H01L29/7817 ,  H01L29/7826 ,  H01L29/7835

摘要： An LDFET is disclosed. A source region is electrically coupled to a source contact. A lightly doped drain (LDD) region has a lower dopant concentration than the source region, and is separated from the source region by a channel. A highly doped drain region forms an electrically conductive path between a drain contact and the LDD region. A gate electrode is located above the channel and separated from the channel by a gate dielectric. A shield plate is located above the gate electrode and the LDD region, and is separated from the LDD region, the gate electrode, and the source contact by a dielectric layer. A control circuit applies a variable voltage to the shield plate that: (1) accumulates a top layer of the LDD region before the transistor is switched on; and (2) depletes the top layer of the LDD region before the transistor is switched off.

摘要翻译： 公开了一种LDFET。 源区域电耦合到源极触点。 轻掺杂漏极（LDD）区域具有比源极区域更低的掺杂剂浓度，并且通过沟道与源极区域分离。 高掺杂漏极区在漏极接触和LDD区之间形成导电路径。 栅极电极位于沟道上方并通过栅极电介质与沟道分离。 屏蔽板位于栅电极和LDD区之上，并通过介电层与LDD区，栅电极和源极接触分离。 控制电路向屏蔽板施加可变电压：（1）在晶体管接通之前累积LDD区的顶层; 和（2）在晶体管截止之前耗尽LDD区的顶层。

公开(公告)号：US20160181420A1

公开(公告)日：2016-06-23

申请号：US14574707

申请日：2014-12-18

申请人： Silanna Semiconductor U.S.A., Inc.

发明人： George Imthurn ,  James Ballard ,  Yashodhan Moghe

IPC分类号： H01L29/78 ,  H01L29/40

CPC分类号： H01L29/402 ,  G01R19/0092 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66681 ,  H01L29/7817 ,  H01L29/7826 ,  H01L29/7835

摘要： An LDFET is disclosed. A source region is electrically coupled to a source contact. A lightly doped drain (LDD) region has a lower dopant concentration than the source region, and is separated from the source region by a channel. A highly doped drain region forms an electrically conductive path between a drain contact and the LDD region. A gate electrode is located above the channel and separated from the channel by a gate dielectric. A shield plate is located above the gate electrode and the LDD region, and is separated from the LDD region, the gate electrode, and the source contact by a dielectric layer. A control circuit applies a variable voltage to the shield plate that: (1) accumulates a top layer of the LDD region before the transistor is switched on; and (2) depletes the top layer of the LDD region before the transistor is switched off.

摘要翻译： 公开了一种LDFET。 源区域电耦合到源极触点。 轻掺杂漏极（LDD）区域具有比源极区域更低的掺杂剂浓度，并且通过沟道与源极区域分离。 高掺杂漏极区在漏极接触和LDD区之间形成导电路径。 栅极电极位于沟道上方并通过栅极电介质与沟道分离。 屏蔽板位于栅电极和LDD区之上，并通过介电层与LDD区，栅电极和源极接触分离。 控制电路向屏蔽板施加可变电压：（1）在晶体管接通之前累积LDD区的顶层; 和（2）在晶体管截止之前耗尽LDD区的顶层。

公开(公告)号：US07470955B2

公开(公告)日：2008-12-30

申请号：US11107084

申请日：2005-04-15

申请人： Jack L. Glenn ,  Troy D. Clear ,  Mark W. Gose ,  Doublas B. Osborn ,  Nicholas T. Campanile

发明人： Jack L. Glenn ,  Troy D. Clear ,  Mark W. Gose ,  Doublas B. Osborn ,  Nicholas T. Campanile

IPC分类号： H01L29/06

CPC分类号： H01L29/7809 ,  H01L27/0722 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/7815 ,  H01L29/7816 ,  H01L29/7826 ,  H03K17/0822

摘要： An integrated circuit (IC) with negative potential protection includes at least one double-diffused metal-oxide semiconductor (DMOS) cell formed in a first-type epitaxial pocket, which is formed in a second-type substrate. The IC also includes a second-type+ isolation ring formed in the substrate to isolate the first-type epitaxial pocket and a first-type+ ring formed through the first-type epitaxial pocket between the second-type+ isolation ring and the DMOS cell.

摘要翻译： 具有负电位保护的集成电路（IC）包括形成在第二型衬底中的第一型外延袋中形成的至少一个双扩散金属氧化物半导体（DMOS）单元。 该IC还包括形成在衬底中以隔离第一型外延袋的第二型+隔离环和通过第二型+隔离环与DMOS电池之间的第一型外延袋形成的第一型+环。

公开(公告)号：US20190067473A1

公开(公告)日：2019-02-28

申请号：US16140864

申请日：2018-09-25

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Jean-Paul EGGERMONT ,  Johan Camiel Julia JANSSENS

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/762 ,  H01L29/10 ,  H01L27/092 ,  H03K17/06 ,  H01L27/06

CPC分类号： H01L29/7826 ,  H01L21/76224 ,  H01L21/823481 ,  H01L21/823493 ,  H01L27/0623 ,  H01L27/0629 ,  H01L27/0922 ,  H01L29/063 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/78 ,  H03K17/063 ,  H03K2217/0009 ,  H03K2217/0018 ,  H03K2217/0027

摘要： An illustrative bidirectional MOSFET switch includes a body region, a buried layer, a gate terminal, and a configuration switch. The body region is a semiconductor of a first type separating a source region and a drain region that are a semiconductor of a second type. The buried layer is a semiconductor of the second type separating the body region from a substrate that is a semiconductor of the first type. The gate terminal is drivable to form a channel in the body region, thereby enabling conduction between the source terminal and the drain terminal. The configuration switch connects the body terminal to the buried layer terminal when the source terminal voltage exceeds the drain terminal voltage.

公开(公告)号：US09755070B2

公开(公告)日：2017-09-05

申请号：US15077927

申请日：2016-03-23

申请人： DELTA ELECTRONICS, INC.

发明人： Chao-Feng Cai ,  Jian-Hong Zeng ,  Zeng Li

IPC分类号： H01L29/78 ,  H01L23/50

CPC分类号： H01L29/7826 ,  H01L23/50 ,  H01L24/20 ,  H01L24/24 ,  H01L2224/04105 ,  H01L2224/18 ,  H01L2924/19104

摘要： A semiconductor packaging structure includes a chip, a first pin, a second pin, and a third pin. The chip includes a first surface, a second surface, a first power switch, and a second switch, and both the first power switch and the second switch include a first terminal and a second terminal. The second surface of the chip is opposite to the first surface of the chip. The first pin does not contact to the second pin. The first terminal of the first power switch of the chip is coupled to the first pin, and the second terminal of the first power switch of the chip is coupled to the third pin. The first terminal of the second power switch of the chip is coupled to the third pin, and the second terminal of the second power switch of the chip is coupled to the second pin.