公开(公告)号：US11038014B2

公开(公告)日：2021-06-15

申请号：US16154704

申请日：2018-10-08

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Yi-Ching Chang ,  Kai-Lou Huang ,  Ying-Chih Lin ,  Gang-Yi Lin

IPC: H01L29/76 ,  H01L29/06 ,  H01L21/027 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/033 ,  H01L21/311

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure, a first dielectric layer, a second dielectric layer, a first plug and two metal lines. The substrate has a shallow trench isolation and an active area, and the gate structure is disposed on the substrate to cover a boundary between the active area and the shallow trench isolation. The first dielectric layer is disposed on the substrate, to cover the gate structure, and the first plug is disposed in the first dielectric layer to directly in contact with a conductive layer of the gate structure and the active area. The second dielectric layer is disposed on the first dielectric layer, with the first plug and the gate being entirely covered by the first dielectric layer and the second dielectric layer. The two metal lines are disposed in the second dielectric layer.

公开(公告)号：US10366889B2

公开(公告)日：2019-07-30

申请号：US15660967

申请日：2017-07-27

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Chieh-Te Chen ,  Yi-Ching Chang

IPC: H01L21/033 ,  H01L21/3213 ,  H01L27/115

Abstract: A method of forming a semiconductor device includes the following steps. First of all, a material layer is formed on a substrate, and a sidewall image transferring process is performed to form plural first mask patterns on the material layer, with the first mask patterns parallel extended along a first direction. Next, a pattern splitting process is performed to remove a portion of the first mask patterns to form plural second openings, with the second openings parallel extended along a second direction, across the first mask patterns. Then, the material layer is patterned by using rest portions of the first mask patterns as a mask to form plural patterns arranged in an array.

公开(公告)号：US20190013321A1

公开(公告)日：2019-01-10

申请号：US15990811

申请日：2018-05-28

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yi-Ching Chang ,  Feng-Yi Chang ,  Fu-Che Lee ,  Chieh-Te Chen

IPC: H01L27/108 ,  G11C11/401

Abstract: A method of forming semiconductor memory device includes the following steps. Firstly, a substrate is provided and the substrate includes a cell region. Then, plural bit lines are disposed within the cell region along a first direction, with each of the bit line includes a tri-layered spacer structure disposed at two sides thereof. Next, plural of first plugs are formed within the cell region, with the first plugs being disposed at two sides of each bit lines. Furthermore, plural conductive patterns are formed in alignment with each first plugs. Following theses, a chemical reaction process is performed to modify the material of a middle layer of the tri-layered spacer structure, and a heat treatment process is performed then to remove the modified middle layer, thereto form an air gap layer within the tri-layered spacer structure.

公开(公告)号：US11244948B2

公开(公告)日：2022-02-08

申请号：US16158317

申请日：2018-10-12

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Yi-Ching Chang ,  Kai-Lou Huang

IPC: H01L27/108

Abstract: A semiconductor device and method of forming the same, the semiconductor device includes a substrate, a first plug, a conductive pad and a capacitor structure. The first plug is disposed on the substrate, and the conductive pad is disposed on the first plug, with the conductive pad including a recessed shoulder portion at a top corner thereof. The capacitor structure is disposed on the conductive pad, to directly in connection with thereto.

公开(公告)号：US20200083325A1

公开(公告)日：2020-03-12

申请号：US16154704

申请日：2018-10-08

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Yi-Ching Chang ,  Kai-Lou Huang ,  Ying-Chih Lin ,  Gang-Yi Lin

IPC: H01L29/06 ,  H01L21/027 ,  H01L29/66 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3213

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure, a first dielectric layer, a second dielectric layer, a first plug and two metal lines. The substrate has a shallow trench isolation and an active area, and the gate structure is disposed on the substrate to cover a boundary between the active area and the shallow trench isolation. The first dielectric layer is disposed on the substrate, to cover the gate structure, and the first plug is disposed in the first dielectric layer to directly in contact with a conductive layer of the gate structure and the active area. The second dielectric layer is disposed on the first dielectric layer, with the first plug and the gate being entirely covered by the first dielectric layer and the second dielectric layer. The two metal lines are disposed in the second dielectric layer.

公开(公告)号：US10734284B2

公开(公告)日：2020-08-04

申请号：US16134976

申请日：2018-09-19

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Ying-Chih Lin ,  Gang-Yi Lin ,  Chieh-Te Chen ,  Yi-Ching Chang

IPC: H01L21/033 ,  H01L21/768 ,  H01L21/308 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/311

Abstract: A method of self-aligned double patterning is disclosed in the present invention, which includes the step of forming multiple mandrels on a hard mask layer and spacers at two sides of each mandrel, forming a protection layer filling between the spacers, removing the mandrels to expose the hard mask layer, and performing an anisotropic etch process using the spacers and the protection layer as an etch mask to remove a portion of hard mask layer, so that a thickness of hard mask layer exposed between the spacers equals to a thickness of hard mask layer under the protection layer.

公开(公告)号：US10700071B1

公开(公告)日：2020-06-30

申请号：US16258657

申请日：2019-01-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Gang-Yi Lin ,  Shih-Fang Tzou ,  Fu-Che Lee ,  Feng-Yi Chang ,  Ying-Chih Lin ,  Kai-Lou Huang ,  Yi-Ching Chang

IPC: H01L21/033 ,  H01L21/308 ,  H01L27/108

Abstract: The present invention provides a method for forming a semiconductor pattern, comprising: firstly, a target layer is provided and a first material layer is formed on the target layer, and then a first pattern is formed on the first material layer, followed by a first self-aligned double pattering step is performed, a plurality of first grooves are formed in the first material layer. Next, a second material layer is formed on the first material layer, and a plurality of second grooves are formed in the second material layer. Next, transferring a pattern of the overlapping portion of the first grooves and the second grooves into the target layer, the target layer includes a plurality of third patterns and a plurality of fourth patterns, an area of each fourth pattern is larger than an area of each third pattern.

公开(公告)号：US20200083224A1

公开(公告)日：2020-03-12

申请号：US16158317

申请日：2018-10-12

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Yi-Ching Chang ,  Kai-Lou Huang

IPC: H01L27/108

Abstract: A semiconductor device and method of forming the same, the semiconductor device includes a substrate, a first plug, a conductive pad and a capacitor structure. The first plug is disposed on the substrate, and the conductive pad is disposed on the first plug, with the conductive pad including a recessed shoulder portion at a top corner thereof. The capacitor structure is disposed on the conductive pad, to directly in connection with thereto.

公开(公告)号：US20190139824A1

公开(公告)日：2019-05-09

申请号：US16134976

申请日：2018-09-19

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Ying-Chih Lin ,  Gang-Yi Lin ,  Chieh-Te Chen ,  Yi-Ching Chang

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/28 ,  H01L21/308

Abstract: A method of self-aligned double patterning is disclosed in the present invention, which includes the step of forming multiple mandrels on a hard mask layer and spacers at two sides of each mandrel, forming a protection layer filling between the spacers, removing the mandrels to expose the hard mask layer, and performing an anisotropic etch process using the spacers and the protection layer as an etch mask to remove a portion of hard mask layer, so that a thickness of hard mask layer exposed between the spacers equals to a thickness of hard mask layer under the protection layer.

公开(公告)号：US20180337186A1

公开(公告)日：2018-11-22

申请号：US16029638

申请日：2018-07-08

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yi-Ching Chang ,  Feng-Yi Chang ,  Fu-Che Lee ,  Chieh-Te Chen

IPC: H01L27/108 ,  H01L21/768

CPC classification number: H01L27/10885 ,  H01L21/7682 ,  H01L21/76897 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a cell region and a peripheral region; forming a bit line structure on the cell region and a gate structure on the peripheral region; forming an interlayer dielectric (ILD) layer around the bit line structure and the gate structure; forming a conductive layer on the bit line structure; performing a first photo-etching process to remove part of the conductive layer for forming storage contacts adjacent two sides of the bit line structure and contact plugs adjacent to two sides of the gate structure; forming a first cap layer on the cell region and the peripheral region to cover the bit line structure and the gate structure; and performing a second photo-etching process to remove part of the first cap layer on the cell region.