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    Electrostatic discharge protection circuit for bypassing an ESD current
    1.
    发明申请
    Electrostatic discharge protection circuit for bypassing an ESD current 审中-公开

    公开(公告)号：US20190229531A1

    公开(公告)日：2019-07-25

    申请号：US15878421

    申请日：2018-01-24

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Yu-Cheng Liao ,  Ting-Yao Lin ,  Ping-Chen Chang ,  Tien-Hao Tang

    IPC: H02H9/04 ,  H02H1/00 ,  H01L27/02

    Abstract: An electrostatic discharge (ESD) protection circuit has a first power node, a second power node, an ESD detect circuit, an ESD device and a voltage controlled switch. The ESD detect circuit is coupled between the first power node and the second power node for detecting an ESD current to output a control signal at a output terminal of the ESD detect circuit. The ESD device is coupled between the first power node and the second power node for leaking the ESD current. The voltage controlled switch is used to couple a body of the ESD device to the second power node according to at least a voltage level of the control signal.

    LAYOUT STRUCTURE FOR ELECTROSTATIC DISCHARGE PROTECTION
    2.
    发明申请
    LAYOUT STRUCTURE FOR ELECTROSTATIC DISCHARGE PROTECTION 有权

    公开(公告)号：US20170084604A1

    公开(公告)日：2017-03-23

    申请号：US14860788

    申请日：2015-09-22

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Pei-Shan Tseng ,  Yu-Cheng Liao ,  Ping-Chen Chang ,  Tien-Hao Tang ,  Kuan-Cheng Su

    IPC: H01L27/02

    CPC classification number: H01L27/0266 ,  H01L27/0207 ,  H01L27/0255 ,  H01L27/1203 ,  H01L28/00

    Abstract: A layout structure is provided. The layout structure includes a substrate, a gate conductive layer, a first doped region having a first conductivity, a second doped region having the first conductivity, and a third doped region having a second conductivity. The gate conductive layer is formed on the substrate. The first doped region the second doped region are formed in the substrate and located at two sides of the gate conductive layer. The third doped region is formed in the substrate and adjacent to the second doped region. The third doped region and the second doped region form a diode. The gate conductive layer, the first doped region, and the third doped region are connected to ground, and the second doped region is connected to an input/output pad.

    Semiconductor structure suitable for electrostatic discharge protection application
    5.
    发明授权
    Semiconductor structure suitable for electrostatic discharge protection application 有权
    半导体结构适用于静电放电保护应用

    公开(公告)号：US09466598B1

    公开(公告)日：2016-10-11

    申请号：US14798564

    申请日：2015-07-14

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Yu-Cheng Liao ,  Yu-Chun Chen ,  Ping-Chen Chang ,  Tien-Hao Tang

    IPC: H01L27/02 ,  H01L29/861

    CPC classification number: H01L27/0255 ,  H01L27/0259 ,  H01L27/0262 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/861 ,  H01L29/87

    Abstract: A semiconductor structure suitable for ESD protection application is provided. The semiconductor structure includes a first well, a second well, a third well, a first fin, a second fin, an anode, a cathode and a first doping region. The first well and the second well are disposed in the third well. The first fin is disposed on the first well. The second fin is disposed on the second well. The anode is disposed on the first fin. The cathode is disposed on the second fin. The first doping region is disposed under the first fin, and separates the first fin from the first well. The first well, the second well, the first fin and the second fin have a first doping type. The third well and the first doping region have a second doping type.

    Abstract translation: 提供了适用于ESD保护应用的半导体结构。 半导体结构包括第一阱，第二阱，第三阱，第一鳍片，第二鳍片，阳极，阴极和第一掺杂区域。 第一口井和第二口井位于第三口井。 第一个翅片放在第一个井上。 第二个翅片设置在第二个孔上。 阳极设置在第一翅片上。 阴极设置在第二散热片上。 第一掺杂区域设置在第一鳍片下方，并且将第一鳍片与第一阱分离。 第一井，第二井，第一鳍和第二鳍具有第一种掺杂类型。 第三阱和第一掺杂区具有第二掺杂类型。

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