公开(公告)号：US20160204230A1

公开(公告)日：2016-07-14

申请号：US15077937

申请日：2016-03-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsiang-Chen Lee ,  Ping-Chia Shih ,  Chi-Cheng Huang ,  Wan-Fang Chung ,  Yu-Chun Chang ,  Je-Yi Su

IPC: H01L29/66 ,  H01L21/033 ,  H01L21/02 ,  H01L21/28 ,  H01L27/115

CPC classification number: H01L29/66833 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/0332 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/42348 ,  H01L29/792 ,  H01L29/7923

Abstract: A method for fabricating semiconductor device is disclosed. Preferably, two hard masks are utilized to define the width of the first gate (may serve for a control gate) and the width of the second gate (may serve for a select gate). The widths are thus well controlled. For example, in an embodiment, the width of the select gate may be adjusted in advance as desired, and the select gate is protected by the second hard mask during an etch process, so as to obtain a select gate which upper portion has an appropriate width. Accordingly the semiconductor device would still have an excellent performance upon miniaturization.

Abstract translation: 公开了半导体器件的制造方法。 优选地，使用两个硬掩模来限定第一栅极的宽度（可用于控制栅极）和第二栅极的宽度（可用于选择栅极）。 因此，宽度被很好地控制。 例如，在一个实施例中，可以根据需要预先调整选择栅极的宽度，并且在蚀刻工艺期间由第二硬掩模保护选择栅极，以便获得选择栅极，其上部具有适当的 宽度。 因此，半导体器件在小型化时仍然具有优异的性能。

公开(公告)号：US09202701B1

公开(公告)日：2015-12-01

申请号：US14572805

申请日：2014-12-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-I Chou ,  Chi-Cheng Huang ,  Yu-Chun Chang ,  Ling-Hsiu Chou ,  Tseng-Fang Dai ,  Jheng-Jie Huang ,  Ping-Chia Shih

IPC: H01L21/336 ,  H01L21/28 ,  H01L27/115

CPC classification number: H01L21/28282 ,  H01L29/66833 ,  H01L29/792

Abstract: A method for manufacturing a silicon-oxide-nitride-oxide-silicon non-volatile memory cell includes following steps. An implant region is formed in a substrate. A first oxide layer, a nitride layer, and a second oxide layer are formed and stacked on the substrate. A density of the second oxide layer is higher than a density of the first oxide layer. A first photoresist pattern is formed on the second oxide layer and corresponding to the implant region. A first wet etching process is then performed to form an oxide hard mask. A second wet etching process is performed to remove the nitride layer exposed by the oxide hard mask to form a nitride pattern. A cleaning process is then performed to remove the oxide hard mask and the first oxide layer exposed by the nitride pattern, and a gate oxide layer is then formed on the nitride pattern.

Abstract translation: 一种用于制造氧化硅 - 氮化物 - 氧化物 - 硅非易失性存储单元的方法包括以下步骤。 在衬底中形成植入区域。 形成第一氧化物层，氮化物层和第二氧化物层并堆叠在基板上。 第二氧化物层的密度高于第一氧化物层的密度。 第一光致抗蚀剂图案形成在第二氧化物层上并对应于植入区域。 然后进行第一湿法蚀刻工艺以形成氧​​化物硬掩模。 执行第二湿法蚀刻工艺以去除由氧化物硬掩模暴露的氮化物层以形成氮化物图案。 然后进行清洁处理以除去由氮化物图案暴露的氧化物硬掩模和第一氧化物层，然后在氮化物图案上形成栅极氧化物层。

公开(公告)号：US20140353739A1

公开(公告)日：2014-12-04

申请号：US13909057

申请日：2013-06-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsiang-Chen Lee ,  Ping-Chia Shih ,  Chi-Cheng Huang ,  Wan-Fang Chung ,  Yu-Chun Chang ,  Je-Yi Su

IPC: H01L29/66 ,  H01L29/792

CPC classification number: H01L29/66833 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/0332 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/42348 ,  H01L29/792 ,  H01L29/7923

Abstract: A semiconductor device including a first gate structure and a second gate structure immediately adjacent to each other with a spacer therebetween. Line width of the top of the second gate structure is not less than that of the bottom thereof. A fabrication method thereof is also disclosed. A transient first gate structure and a temporary gate structure are formed by etching through a first hard mask. A second gate structure is formed between a first spacer and a second spacer opposite to each other and disposed respectively on the transient first gate structure and temporary gate structure. The second gate structure is covered with a second hard mask. An etch process is performed through a patterned photoresist layer to remove exposed first hard mask and temporary gate structure and to partially remove exposed portion of first hard mask and transient first gate structure to form the first gate structure.

Abstract translation: 一种半导体器件，包括彼此紧邻的第一栅极结构和第二栅极结构，其间具有间隔物。 第二栅极结构的顶部的线宽不小于其底部的线宽。 还公开了其制造方法。 通过蚀刻穿过第一硬掩模形成瞬态第一栅极结构和临时栅极结构。 第二栅极结构形成在第一间隔物和彼此相对的第二间隔物之间​​，分别设置在瞬态第一栅极结构和临时栅极结构上。 第二个门结构用第二个硬掩模覆盖。 通过图案化的光致抗蚀剂层进行蚀刻处理以去除暴露的第一硬掩模和临时栅极结构，并且部分地去除第一硬掩模和瞬态第一栅极结构的暴露部分以形成第一栅极结构。

公开(公告)号：US09397202B1

公开(公告)日：2016-07-19

申请号：US15077937

申请日：2016-03-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsiang-Chen Lee ,  Ping-Chia Shih ,  Chi-Cheng Huang ,  Wan-Fang Chung ,  Yu-Chun Chang ,  Je-Yi Su

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/28 ,  H01L27/115 ,  H01L21/02 ,  H01L21/033

CPC classification number: H01L29/66833 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/0332 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/42348 ,  H01L29/792 ,  H01L29/7923

Abstract: A method for fabricating semiconductor device is disclosed. Preferably, two hard masks are utilized to define the width of the first gate (may serve for a control gate) and the width of the second gate (may serve for a select gate). The widths are thus well controlled. For example, in an embodiment, the width of the select gate may be adjusted in advance as desired, and the select gate is protected by the second hard mask during an etch process, so as to obtain a select gate which upper portion has an appropriate width. Accordingly the semiconductor device would still have an excellent performance upon miniaturization.

Abstract translation: 公开了半导体器件的制造方法。 优选地，使用两个硬掩模来限定第一栅极的宽度（可用于控制栅极）和第二栅极的宽度（可用于选择栅极）。 因此，宽度被很好地控制。 例如，在实施例中，可以根据需要预先调整选择栅极的宽度，并且在蚀刻工艺期间选择栅极被第二硬掩模保护，以便获得选择栅极，其上部具有适当的 宽度。 因此，半导体器件在小型化时仍然具有优异的性能。

公开(公告)号：US09412851B2

公开(公告)日：2016-08-09

申请号：US14138153

申请日：2013-12-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Chun Chang ,  Ping-Chia Shih ,  Chi-Cheng Huang ,  Kuo-Lung Li ,  Kun-I Chou ,  Chung-Che Huang ,  Chia-Cheng Hsu ,  Mu-Jia Liu

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L29/66 ,  H01L27/115

CPC classification number: H01L29/66833 ,  H01L27/1157 ,  H01L27/11573

Abstract: A method for fabricating a semiconductor device includes forming a patterned multi-layered dielectric film on a substrate; forming a patterned stack on the patterned multi-layered dielectric film so that an edge of the patterned multi-layered dielectric film is exposed from the patterned stack; forming a cover layer to cover a part of the substrate and expose the patterned stack and the exposed edge of the patterned multi-layered dielectric film; removing at least a part of the exposed edge of the patterned multi-layered dielectric film by using the cover layer and the patterned stack as an etching mask; and performing an ion implantation process by using the cover layer as an etching mask so as to form a doped region.

Abstract translation: 一种制造半导体器件的方法包括在衬底上形成图案化的多层电介质膜; 在图案化的多层电介质膜上形成图案化的叠层，使得图案化的多层电介质膜的边缘从图案化的叠层露出; 形成覆盖层以覆盖基板的一部分并暴露图案化的叠层和图案化多层电介质膜的暴露边缘; 通过使用覆盖层和图案化叠层作为蚀刻掩模去除图案化的多层电介质膜的暴露边缘的至少一部分; 以及通过使用覆盖层作为蚀刻掩模进行离子注入工艺以形成掺杂区域。

公开(公告)号：US20150179748A1

公开(公告)日：2015-06-25

申请号：US14138153

申请日：2013-12-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Chun Chang ,  Ping-Chia Shih ,  Chi-Cheng Huang ,  Kuo-Lung Li ,  Kun-I Chou ,  Chung-Che Huang ,  Chia-Cheng Hsu ,  Mu-Jia Liu

IPC: H01L29/423 ,  H01L29/66

CPC classification number: H01L29/66833 ,  H01L27/1157 ,  H01L27/11573

Abstract: A method for fabricating a semiconductor device includes forming a patterned multi-layered dielectric film on a substrate; forming a patterned stack on the patterned multi-layered dielectric film so that an edge of the patterned multi-layered dielectric film is exposed from the patterned stack; forming a cover layer to cover a part of the substrate and expose the patterned stack and the exposed edge of the patterned multi-layered dielectric film; removing at least a part of the exposed edge of the patterned multi-layered dielectric film by using the cover layer and the patterned stack as an etching mask; and performing an ion implantation process by using the cover layer as an etching mask so as to form a doped region.

Abstract translation: 一种制造半导体器件的方法包括在衬底上形成图案化的多层电介质膜; 在图案化的多层电介质膜上形成图案化的叠层，使得图案化的多层电介质膜的边缘从图案化的叠层露出; 形成覆盖层以覆盖基板的一部分并暴露图案化的叠层和图案化多层电介质膜的暴露边缘; 通过使用覆盖层和图案化叠层作为蚀刻掩模去除图案化的多层电介质膜的暴露边缘的至少一部分; 以及通过使用覆盖层作为蚀刻掩模进行离子注入工艺以形成掺杂区域。

公开(公告)号：US09331183B2

公开(公告)日：2016-05-03

申请号：US13909057

申请日：2013-06-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsiang-Chen Lee ,  Ping-Chia Shih ,  Chi-Cheng Huang ,  Wan-Fang Chung ,  Yu-Chun Chang ,  Je-Yi Su

IPC: H01L29/792 ,  H01L29/66 ,  H01L21/28 ,  H01L29/423 ,  H01L27/115

CPC classification number: H01L29/66833 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/0332 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/42348 ,  H01L29/792 ,  H01L29/7923

Abstract: A semiconductor device including a first gate structure and a second gate structure immediately adjacent to each other with a spacer therebetween. Line width of the top of the second gate structure is not less than that of the bottom thereof. A fabrication method thereof is also disclosed. A transient first gate structure and a temporary gate structure are formed by etching through a first hard mask. A second gate structure is formed between a first spacer and a second spacer opposite to each other and disposed respectively on the transient first gate structure and temporary gate structure. The second gate structure is covered with a second hard mask. An etch process is performed through a patterned photoresist layer to remove exposed first hard mask and temporary gate structure and to partially remove exposed portion of first hard mask and transient first gate structure to form the first gate structure.

Abstract translation: 一种半导体器件，包括彼此紧邻的第一栅极结构和第二栅极结构，其间具有间隔物。 第二栅极结构的顶部的线宽不小于其底部的线宽。 还公开了其制造方法。 通过蚀刻穿过第一硬掩模形成瞬态第一栅极结构和临时栅极结构。 第二栅极结构形成在第一间隔物和彼此相对的第二间隔物之间​​，分别设置在瞬态第一栅极结构和临时栅极结构上。 第二个门结构用第二个硬掩模覆盖。 通过图案化的光致抗蚀剂层进行蚀刻处理以去除暴露的第一硬掩模和临时栅极结构，并且部分地去除第一硬掩模和瞬态第一栅极结构的暴露部分以形成第一栅极结构。